3-D inductor and transformer devices in MRAM embedded integrated circuits

• US 20060273418A1
• Filed: 06/07/2005
• Published: 12/07/2006
• Est. Priority Date: 06/07/2005
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Baird, Robert W., Engel, Bradley N., Durlam, Mark A., Chung, Young Sir
• Granted Patent: US 7,262,069 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 19/04 Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range resonant circuits H03H
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Abstract

An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and at least one inductance element formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as the program lines of the MRAM architecture. Any available metal layer in addition to the program line layers can be added to the inductance element to enhance its efficiency. The concurrent fabrication of the MRAM architecture and the inductance element facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

Claims

1. An integrated circuit device comprising:

a substrate;

a magnetic random access memory (“

MRAM”

) architecture formed on said substrate,

said MRAM architecture comprising;

at least one digit line formed from a first metal layer;

at least one bit line formed from a second metal layer; and

a magnetic tunnel junction core formed between said first metal layer and said second metal layer; and

an inductance element formed on said substrate from at least one of said first metal layer or said second metal layer.

2. An integrated circuit according to claim 1, said inductance element comprising a spiral inductor formed from at least one of said first metal layer or said second metal layer.

3. An integrated circuit according to claim 1, said inductance element comprising a dual spiral inductor having a first spiral element formed from said first metal layer, a second spiral element formed from said second metal layer, and a number of conductive vias coupled between said first spiral element and said second spiral element.

4. An integrated circuit according to claim 1, further comprising a magnetic shield layer formed over said inductance element.

5. An integrated circuit according to claim 4, further comprising a passivation layer formed over said inductance element, said magnetic shield layer contacting said passivation layer for use as a heat sink.

6. An integrated circuit according to claim 1, said inductance element comprising a transformer, said transformer comprising a primary winding formed from one of said first metal layer or said second metal layer, and a secondary winding formed from the other of said first metal layer or said second metal layer.

7. An integrated circuit according to claim 6, further comprising a magnetic transformer core layer formed over said primary winding and over said secondary winding.

8. An integrated circuit according to claim 6, further comprising a magnetic transformer core layer formed between said primary winding and said secondary winding.

9. An integrated circuit according to claim 1, wherein:

each digit line comprises a conductive digit element and first cladding formed from a magnetic material, said first cladding partially surrounding said conductive digit element;

each bit line comprises a conductive bit element and second cladding, formed from said magnetic material, said second cladding partially surrounding said conductive bit element; and

said inductance element comprises a conductive inductor line and third cladding, formed from said magnetic material, said third cladding partially surrounding said conductive inductor line.

10. A method of forming an integrated circuit device, said method comprising:

forming, on a substrate, at least one digit line from a first metal layer;

forming, on said substrate, at least one bit line from a second metal layer;

forming, on said substrate and between said first metal layer and said second metal layer, a magnetic tunnel junction core, said at least one digit line, said at least one bit line, and said magnetic tunnel junction core comprising a magnetic random access memory (“

MRAM”

) architecture; and

forming, on said substrate, an inductance element from at least one of said first metal layer or said second metal layer.

11. A method according to claim 10, wherein forming said inductance element comprises forming a spiral inductor from at least one of said first metal layer, concurrently with said at least one digit line, or said second metal layer, concurrently with said at least one bit line.

12. A method according to claim 10, wherein forming said inductance element comprises:

forming a first spiral element from said first metal layer concurrently with said at least one digit line;

forming a second spiral element from said second metal layer concurrently with said at least one bit line; and

forming a number of conductive vias between said first spiral element and said second spiral element.

13. A method according to claim 10, wherein forming said inductance element comprises:

forming a first spiral element from said first metal layer concurrently with said at least one digit line;

forming a second spiral element from said second metal layer concurrently with said at least one bit line;

forming at least one additional spiral element from at least one additional metal layer other than said first metal layer and said second metal layer; and

forming a number of conductive vias between said first spiral element, said second spiral element, and said at least one additional spiral element.

14. A method according to claim 10, further comprising forming a magnetic shield layer over said inductance element.

15. A method according to claim 10, wherein forming said inductance element comprises:

forming a primary transformer winding from said first metal layer concurrently with said at least one digit line; and

forming a secondary transformer winding from said second metal layer concurrently with said at least one bit line.

16. An integrated circuit device comprising:

a substrate;

a magnetic random access memory (“

MRAM”

) array on said substrate, said MRAM array comprising program lines formed from a metal layer; and

an inductance element on said substrate, said inductance element having a feature formed from said metal layer concurrently with said program lines.

17. An integrated circuit device according to claim 16, said inductance element comprising a spiral inductor formed from said metal layer concurrently with said program lines.

18. An integrated circuit device according to claim 16, said inductance element comprising a transformer having a winding formed from said metal layer concurrently with said program lines.

19. An integrated circuit device according to claim 16, wherein:

each of said program lines comprises a conductive element and first magnetic cladding at least partially surrounding said conductive element; and

said inductance element comprises a conductive inductor line and second magnetic cladding at least partially surrounding said conductive inductor line, said conductive inductor line being formed concurrently with said conductive element and said second magnetic cladding being formed concurrently with said first magnetic cladding.

20. An integrated circuit device according to claim 16, further comprising at least one additional circuit component on said substrate, said at least one additional circuit component being formed below said inductance element.