SEMICONDUCTOR DEVICE FOR ACCOMMODATING LARGE CHIPS, FABRICATION METHOD THEREOF, AND CARRIER USED IN THE SEMICONDUCTOR DEVICE

• US 20060273442A1
• Filed: 10/13/2005
• Published: 12/07/2006
• Est. Priority Date: 06/07/2005
• Status: Active Grant

• Current Assignee: Siliconware Precision Industries Co., Ltd.
• Original Assignee: Siliconware Precision Industries Co., Ltd.
• Inventors: Huang, Chien-Ping, Tsai, Yu-Chieh, Tsai, Yun-Lung, Chen, Chien-Chih
• Granted Patent: US 7,443,016 B2
• Time in Patent Office: Days
• US Class Current: 257/687
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/15162 : Top view
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 2201/09127 : PCB or component having an integral separable or breakable part
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence

Abstract

A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

Claims

1. A semiconductor device, comprising:

a lid having a chamfer; and

;

a package covered by the lid, the package comprising;

a substrate having a slanted side;

at least one chip and at least one passive component, which are mounted on a surface of the substrate, wherein the chip is electrically connected to the substrate via a plurality of conductive elements; and

an encapsulant formed on the surface of the substrate for encapsulating the at least one chip, the at least one passive component and the conductive elements, the encapsulant being formed with a cutaway corner corresponding to the slanted side of the substrate, such that a portion on the surface of the substrate located between the slanted side thereof and the cutaway corner of the encapsulant is exposed from the encapsulant and the remaining portion of the surface of the substrate is covered by the encapsulant.

2. The semiconductor device of claim 1, wherein with the lid being mounted to the package, the slanted side of the substrate is coupled to the chamfer of the lid.

3. The semiconductor device of claim 1, wherein a side of the encapsulant is coplanar with a side of the substrate.

4. The semiconductor device of claim 1, wherein a side of the encapsulant is slanted inwardly from a side of the substrate to make cross-section of the encapsulant have a wedge shape.

5. The semiconductor device of claim 1, wherein the slanted side of the substrate has a linear shape.

6. The semiconductor device of claim 1, wherein the slanted side of the substrate has a linear shape with at least one turning point.

7. The semiconductor device of claim 1, wherein the slanted side of the substrate has an arc shape.

8. The semiconductor device of claim 1, wherein the slanted side of the substrate has an arc shape with at least one turning point.

9. The semiconductor device of claim 1, wherein the slanted side of the substrate conforms in shape to the chamfer of the lid.

10. The semiconductor device of claim 1, wherein the conductive elements are bonding wires.

11. A fabrication method of a semiconductor device, comprising the steps of:

preparing a carrier having at least one opening, the carrier comprising at least one substrate, wherein a portion of the substrate is connected to a slanted side of the at least one opening;

mounting at least one chip and at least one passive component on the substrate of the carrier;

electrically connecting the chip to the substrate;

performing a molding process to form an encapsulant on the carrier for encapsulating the at least one chip and the at least one passive component, wherein the encapsulant has a side including a portion corresponding to the slanted side of the opening of the carrier and a portion corresponding to a side of the substrate, and the portion of the side of the encapsulant is at least not smaller than the corresponding side of the substrate, and wherein the encapsulant is formed with a cutaway corner corresponding to the slanted side of the opening of the carrier, and a predetermined distance is formed between the cutaway corner of the encapsulant and the slanted side of the opening;

performing linear cutting on the carrier along sides of the substrate to form a package having a size identical to surface area of the substrate, wherein the portion of the substrate connected to the slanted side of the opening is formed as a slanted side of the substrate, and a portion of the substrate located between the slanted side thereof and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion of the substrate; and

mounting a lid having a chamfer to the package to form the semiconductor device, wherein the slanted side of the substrate is coupled to the chamfer of the lid.

12. The fabrication method of claim 11, wherein the opening is formed by a punching technique.

13. The fabrication method of claim 11, wherein the opening is formed by a routering technique.

14. The fabrication method of claim 11, wherein the opening has a shape selected from the group consisting of right triangle, obtuse triangle, acute triangle, and equilateral triangle, and a portion of the slanted side of the opening remaining after the linear cutting step is formed as the slanted side of the substrate.

15. The fabrication method of claim 11, wherein the opening has a semicircular or similar shape, and the slanted side thereof is a linear side, such that a portion of the slanted side of the opening remaining after the linear cutting step is formed as the slanted side of the substrate.

16. The fabrication method of claim 11, wherein the slanted side of the opening is a linear side such that the slanted side of the substrate is a linear side after forming the package.

17. The fabrication method of claim 11, wherein the slanted side of the opening is a non-linear side such that the slanted side of the substrate is a non-linear side after forming the package.

18. The fabrication method of claim 17, wherein the slanted side of the opening comprises at least one turning point.

19. The fabrication method of claim 18, wherein with the slanted side of the opening comprising the at least one turning point, the opening is shaped as a triangle, a semicircle, or any other shape.

20. The fabrication method of claim 11, wherein the slanted side of the opening is not smaller than the slanted side of the substrate, such that the slanted side of the substrate is not subjected to linear cutting in the linear cutting step.

21. The fabrication method of claim 11, wherein after the encapsulant is formed, sides of the encapsulant are located outside the sides of the substrate, such that the encapsulant covers an area on the carrier larger than the surface area of the substrate except the exposed portion of the substrate, and a part of the encapsulant that exceeds the substrate is removed in the linear cutting step.

22. The fabrication method of claim 21, wherein the sides of the substrate except the slanted side thereof are coplanar with the sides of the encapsulant formed on the substrate in the package obtained in the linear cutting step.

23. The fabrication method of claim 11, wherein after the encapsulant is formed, sides of the encapsulant except the cutaway corner thereof are aligned with the sides of the substrate, such that the encapsulant covers the entire surface area of the substrate except the exposed portion thereof, and in the linear cutting step, only a part of the carrier located outside the substrate is removed without cutting the encapsulant.

24. The fabrication method of claim 23, wherein the sides of the encapsulant except the cutaway corner thereof are slanted inwardly from the sides of the substrate in the package obtained in the linear cutting step, such that cross-section of the encapsulant formed on the substrate has a wedge shape.

25. A carrier for a semiconductor device, comprising a rectangular circuit board, the circuit board being formed with at least one opening and comprising at least one substrate having a slanted side, wherein the slanted side of the substrate corresponds to a slanted side of the opening.

26. The carrier of claim 25, wherein the slanted side of the opening is not shorter in length than the slanted side of the substrate.

27. The carrier of claim 25, wherein the opening has a shape selected from the group consisting of right triangle, obtuse triangle, acute triangle, equilateral triangle, semicircle, and similar shape.

28. The carrier of claim 25, wherein the slanted side of the substrate is a linear side.

29. The carrier of claim 25, wherein the slanted side of the substrate is a linear side having at least one turning point.

30. The carrier of claim 25, wherein the slanted side of the substrate is an arc side.

31. The carrier of claim 25, wherein the slanted side of the substrate is an arc side having at least one turning point.

32. The carrier of claim 25, wherein at least one substrate comprises a plurality of the substrates spaced apart from one another.