Method of designing an application specific probe card test system

• US 20060273809A1
• Filed: 06/13/2006
• Published: 12/07/2006
• Est. Priority Date: 04/21/2004
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Henson, Roy J., Chraft, Matthew E.
• Granted Patent: US 8,581,610 B2
• Time in Patent Office: Days
• US Class Current: 324/750.50
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A method is provided for design and programming of a probe card with an on-board programmable controller in a wafer test system. Consideration of introduction of the programmable controller is included in a CAD wafer layout and probe card design process. The CAD design is further loaded into the programmable controller, such as an FPGA to program it: (1) to control direction of signals to particular ICs, even during the test process (2) to generate test vector signals to provide to the ICs, and (3) to receive test signals and process test results from the received signals. In some embodiments, burn-in only testing is provided to limit test system circuitry needed so that with a programmable controller on the probe card, text equipment external to the probe card can be eliminated or significantly reduced from conventional test equipment.

Claims

1. A method of programming a test system to perform testing of integrated circuits (ICs), the method comprising:

providing code to a memory on a probe card, the probe card comprising a plurality of probes, the code being readable by a programmable controller on the probe card to control the provision of test signals from channels of a test system controller through the probes to the ICs, wherein an interconnect relation between channels of a test system controller and the plurality of probes is configurable via the code.

2. The method of claim 1, wherein the programmable controller comprises a Field Programmable Gate Array (FPGA), and the code is readable to configure the FPGA to selectively route signals from individual ones of the channels of the test system controller to different ones of the plurality of probes on the probe card.

3. The method of claim 2, wherein the FPGA selectively routes signals from individual ones of the channels to different Devices Under Test (DUTs) formed by the ICs.

4. The method of claim 1, wherein the code is readable by the programmable controller to enable the programmable controller to generate test signals and apply the test signals from the probe card to the ICs.

5. The method of claim 1, wherein the code is further readable by the programmable controller to enable the programmable controller to process test signal results received from ICs by the probe card, and to provide the processed results from the probe card to a user interface.

6. The method of claim 5, wherein the programmable controller comprises at least one of a field programmable gate array (FPGA), a digital signal processor (DSP), and a microprocessor.

7. A method of claim 1 wherein the programmable controller is provided on a daughter card attached to a main PCB of the probe card, the programmable controller providing test signals in a serial manner from the daughter card to the main PCB, the method further comprising:

converting the test signals received from the programmable controller from serial to parallel on the main PCB; and

distributing the test signals to the probes.

8. The method of claim 1, wherein a code is derived from a Computer Aided Design (CAD) system.

9. The method of claim 8, wherein interconnects between the probes and the IC are configurable based on the CAD.

10. The method of claim 1, wherein the code comprises a computer readable medium for designing interconnects between the channels of the test system controller and the probes of the probe card, the method further comprising:

(a) providing a cell library of structural component cells including the IC components for the ICs to be tested as well as components that can be included in a probe card, the cell library including a structural model and a behavior model for the structural component cells, the structural model describing a layout of the corresponding structural component cell; and

(b) providing the cell library with interconnect component cells each for forming a signal path between at least one of the structural component cells and at least one of another of the structural component cells, wherein each of the interconnect component cells includes structural and behavioral models of its corresponding interconnect system component.

11. The method of claim 10 further comprising the steps of:

(c) selecting the structural component cells to be included in said ICs to be tested and the probe card and selecting the interconnect component cells;

(d) creating a behavioral model of said ICs to be tested and said probe card based on behavioral models included in at least one of said interconnect component cells and the structural component cells selected at step (c), and

(e) employing said behavioral model created at step (d) to simulate a behavior of said ICs to be tested and said probe card when communication occurs between the probe card and said the ICs to be tested.

12. The method of claim 11 further comprising the steps of:

(f) generating a probe card structural model based on the programmable components on the probe card and interconnect component cells selected at step (c), and

(g) fabricating said probe card in accordance with said probe card structural model.

13. The method of claim 11, wherein the step (c) comprises determining the configuration of an FPGA on the probe card to selectively direct signals between the probe card and the ICs to be tested, the method further comprising:

(f) programming the FPGA on the probe card based on the configuration determined in step (c).

14. The method of claim 11, further comprising the step of:

(f) programming a programmable controller on the probe card to generate test signals to provide from the probe card to the ICs to be tested based on the behavioral model of step (d).

15. The method of claim 14, further comprising the step of:

(h) programming a programmable controller on the probe card to determine test results based on signals received from ICs to be tested, the programming being based on the behavioral model of step (d).

16. The method of claim 3, wherein the programmable controller of the probe card is configured to send program and erase voltages to provide the signals for burn-in to ICs that form devices under test (DUTs), the DUTs comprising memory devices.

17. The method of claim 16, wherein the probe card is configured to only transmit the signals to provide for the burn-in.

18. The method of claim 16, wherein serial test signals are provided to at least one serial port of each of the DUTs.

19. The method of claim 16, wherein the DUTs comprise at least one of DRAM, SRAM, SDRAM, MPUs and Flash.

20. The method of claim 16, wherein the programmable controller on the probe card includes circuitry comprising:

a memory storing program and erase voltage control signals for providing to the DUTs to perform burn-in testing;

an address counter connected to the memory to provide a sequence of addresses to the memory so that the memory provides a sequence of the control values to the DUTs to perform burn-in testing;

a microcontroller for storing data in the memory and for providing signals to control the address counter to enable it to send the sequence of addresses to the memory; and

output buffers connected between the memory and channels on the probe card, each output buffer providing the control signals for one of the DUTs.

21. The method of claim 16, wherein the programmable controller comprises a Field Programmable Gate Array (FPGA), the method further comprising partially reprogramming the FPGA during the burn-in.

22. A method to perform testing of integrated circuits (ICs), the method comprising:

partially reconfiguring a Field Programmable Gate Array (FPGA) on a probe card during testing of the ICs, the probe card comprising a plurality of probes, the FPGA being reconfigured to control the provision of test signals from individual channels of a test system controller to different ones of the probes to the ICs during the testing.

23. A probe card system comprising:

a probe card comprising;

a substrate supporting probes;

a programmable controller controlling the provision of test signals from channels of a test system controller through the probes for providing to Devices Under Test (DUTs); and

a memory device for storing code to configure the programmable controller; and

a Computer Aided Design (CAD) system for determining a design for programming the memory device to selectively route signals from individual ones of the test channels to different DUTs as determined by a design of the DUTs.

24. The probe card system of claim 23, wherein the programmable controller comprises a Field Programmable Gate Array (FPGA).

25. The probe card system of claim 23, wherein the CAD system further determines the layout of the DUTs and selects the routing of signals based on the layout determined for the DUTs.

26. The probe card system of claim 25, wherein the CAD system further provides a design of circuit elements for programming into the programmable controller based on the layout determined for the DUTs.

27. A DUT tested by the probe card system of claim 23.