System and method for improved time-interleaved analog-to-digital converter arrays
First Claim
1. A method for reducing non-uniform sample mismatch in a time-interleaved analog-to-digital converter (TI-ADC) array, the method comprising:
- adjusting a sampling clock delay imparted by an adjustable delay in each channel of a plurality of channels in the TI-ADC array in which the channels are utilized in a constant cyclic order to reduce a measured sample mismatch; and
randomly switching between two sampling clock delays imparted by the adjustable delay in each channel to reduce a residual skew, wherein the two delays span an actual delay that would bring the measured sample mismatch substantially to zero.
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Abstract
System and method for improved time-interleaved analog-to-digital converter arrays which reduces sampling mismatch distortion found in prior art arrays. There may be two causes of non-uniform sampling mismatch in a TI-ADC array, a mismatch due to skew and a mismatch due to clock jitter. To minimize non-uniform sampling mismatch, the mismatch due to skew can be addressed. A preferred embodiment comprises adjusting a delay imparted on the sampling clock by an adjustable delay in each channel of a plurality of channels in the TI-ADC array to minimize skew and randomly switching between two delays that span a zero-skew delay to reduce residual skew in each channel and thus eliminate (or reduce) frequency domain tones caused by non-uniform sampling mismatch.
52 Citations
20 Claims
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1. A method for reducing non-uniform sample mismatch in a time-interleaved analog-to-digital converter (TI-ADC) array, the method comprising:
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adjusting a sampling clock delay imparted by an adjustable delay in each channel of a plurality of channels in the TI-ADC array in which the channels are utilized in a constant cyclic order to reduce a measured sample mismatch; and
randomly switching between two sampling clock delays imparted by the adjustable delay in each channel to reduce a residual skew, wherein the two delays span an actual delay that would bring the measured sample mismatch substantially to zero. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A time-interleaved analog-to-digital converter (TI-ADC) array comprising:
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a plurality of channels, each channel coupled to a signal input, wherein each channel comprises a sample and hold circuit (SHC) coupled to the signal input, the SHC configured to capture a signal at the signal input and provide the captured signal at an output;
an analog-to-digital converter (ADC) coupled to the SHC, the ADC configured to convert an analog signal at an input into a digital representation of the analog signal;
the TI-ADC array further comprising, a plurality of adjustable delays coupled to a clock signal source, each adjustable delay coupled to a SHC of a channel in the plurality of channels, each adjustable delay configured to impart a delay onto a signal at a first input, wherein the delay imparted by the adjustable delay is based upon a signal at a second input and wherein the clock signal source activates the channels in a constant cyclic order; and
a multiplexer having an input coupled to an ADC from each channel in the plurality of channels, the multiplexer configured to selectively couple an output from an ADC to a digital signal output of the TI-ADC array. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A system for reducing non-uniform sample mismatch in a time-interleaved analog-to-digital converter (TI-ADC) array, the system comprising:
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a means for reducing a clock skew between clock signals in each channel of a plurality of channels in the TI-ADC array in which the channels are utilized in a constant cyclic order; and
a means for randomly switching between delays imparted to the clock signal in each channel. - View Dependent Claims (18, 19, 20)
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Specification