Method and apparatus to reduce latency and improve throughput of input/output data in a processor

• US 20060282560A1
• Filed: 06/08/2005
• Published: 12/14/2006
• Est. Priority Date: 06/08/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Vasudevan, Anil, Bell, D. Michael
• Granted Patent: US 7,480,747 B2
• Time in Patent Office: Days
• US Class Current: 710/33
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

Some embodiments include apparatus and method to transfer data directly between an input/output device and a processor to reduce latency and improve throughput of the processor. Other embodiments are described and claimed.

Claims

1. A method comprising:

receiving at least one packet at an input/output device; and

transferring at least a portion of the packet between a processor and the input/output device without transferring the portion of the packet to a memory device coupled to the processor.

2. The method of claim 1, wherein transferring at least the portion of the packet is performed without accessing a cache memory circuit of the processor to search for information associated with the packet.

3. The method of claim 2, wherein the processor processes the portion of the packet without receiving from the input/output device an interrupt request associated with the packet.

4. The method of claim 1, wherein the packet includes a header and a payload, and wherein transferring at least the portion of the packet includes transferring the header between a register circuit of the processor and the input/output device.

5. The method of claim 4, wherein transferring at least the portion of the packet further includes transferring the payload between register circuit of the processor and the input/output device, bypassing the memory device.

6. The method of claim 1, wherein the packet includes a header and a payload, wherein transferring at least the portion of the packet includes transferring the header between a register circuit of the processor and the input/output device, and wherein the payload is transferred between a cache memory circuit of the processor and the input/output device, bypassing the memory device.

7. The method of claim 1, wherein the packet includes a header and a payload, wherein transferring at least the portion of the packet includes transferring the header from the input/output device to a register circuit of the processor, and wherein the payload is transferred from the input/output device to the memory device.

8. The method of claim 1, wherein a protocol of the packet is complied with TCP/IP (Transport Control Protocol/Internet Protocol).

9. The method of claim 1, wherein further comprising:

transferring between a register circuit of the processor and the input/output a packet descriptor associated with the packet without transferring the packet descriptor to the memory device.

10. An apparatus comprising:

a register circuit to receive at least a portion of the packet from an input/output device; and

a processing unit to process the portion of the packet based on instructions in the processing unit, the processing unit and the register circuit residing on a processor, wherein the portion of the packet is placed directly into the register circuit of the processor, bypassing a memory device coupled to the processor.

11. The apparatus of claim 10, wherein the processor includes a cache memory circuit, and wherein the processing unit is configured to process the portion of the packet without searching the cache memory circuit for information associated with the packet.

12. The apparatus of claim 11, wherein the processing unit is configured to process the portion of the packet without receiving from the input/output device an interrupt request associated with the packet.

13. The apparatus of claim 10, wherein the register circuit is configured to receive a payload of the packet, wherein the payload and the portion of the packet form an entire packet, and wherein the payload is placed directly into the register circuit of the processor, bypassing the memory device.

14. The apparatus of claim 13, wherein the register circuit is configured to send at least one outgoing packet directly to the input/output device, bypassing the memory device.

15. The apparatus of claim 10, wherein the processor includes a cache memory circuit configured to receive a payload of the packet, wherein the payload and the portion of the packet form an entire packet, and wherein the payload is sent only to the cache memory circuit of the processor, bypassing the memory device.

16. The apparatus of claim 15, wherein the cache memory circuit is configured to send at least one outgoing payload directly to the input/output device, bypassing the memory device.

17. The apparatus of claim 10, wherein the processor includes a number of terminals to connect the processor directly to the input/output device via a connection to allow the processor to communicate directly with the input/output device via the connection.

18. The apparatus of claim 10, wherein the processor includes a number of terminals to indirectly connect the processor to the input/output device via a shared interconnection.

19. A system comprising:

a network interface device to receive at least one packet;

a dynamic random access memory (DRAM) device; and

a processor coupled to the memory device and to the network interface device, the processor including a register circuit to receive at least a portion of the packet, and a processing unit to process the portion of the packet, wherein the portion of the packet is placed directly into the register circuit, bypassing the memory device.

20. The system of claim 19 further comprising a connection connected directly between the network interface device and the processor.

21. The system of claim 19, wherein the processor further includes a cache memory circuit, and wherein the processing unit is configured to process the portion of the packet without searching the cache memory circuit for information associated with the packet.

22. The system of claim 21, wherein the processing unit is configured to process the portion of the packet without receiving an interrupt request originated by the network interface device.

23. The system of claim 19, wherein the register circuit is configured to receive a payload of the packet, wherein the payload and the portion of the packet form an entire packet, and wherein the payload is placed into the register circuit of the processor, bypassing the memory device.

24. The system of claim 21, wherein the cache memory circuit is configured to receive a payload of the packet, wherein the payload and the portion of the packet form an entire packet, and wherein the payload is placed only into the cache memory circuit of the processor, bypassing the memory device.

25. The system of claim 19 further includes a data movement engine to place a payload of the packet into the memory device.

26. An article including a machine-accessible medium having associated information, wherein the information, when accessed, results in a machine performing:

receiving at least one packet at an input/output device; and

transferring at least a portion of the packet between a processor and the input/output device without transferring the portion of packet to a memory device coupled to the processor.

27. The article of claim 26, wherein transferring at least the portion of the packet is performed without accessing a cache memory circuit of the processor to search for information associated with the packet.

28. The article of claim 27, wherein the processor processes the portion of the packet without receiving from the input/output device an interrupt request associated with the packet.

29. The article of claim 26, wherein the packet includes a header and a payload, and wherein transferring at least the portion of the packet includes transferring the header between a register circuit of the processor and the input/output device.

30. The article of claim 29, wherein transferring at least the portion of the packet further includes transferring the payload between register circuit of the processor and the input/output device, bypassing the memory device.