Digital transmitter

• US 20060291586A1
• Filed: 08/31/2006
• Published: 12/28/2006
• Est. Priority Date: 06/20/1997
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Dally, William J.
• Granted Patent: US 7,602,857 B2
• Time in Patent Office: Days
• US Class Current: 375/296
• CPC Class Codes: H04B 1/0483 Transmitters with multiple parallel paths
• CPC Class Codes: H04B 1/1081 Reduction of multipath noise by equalising H04B7/005
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 3/04 Control of transmission; Equalising
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03025 using a two-tap delay line
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 27/01 Equalisers baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005

Abstract

An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

Claims

1. A component comprising:

a semiconductor chip;

a processor within the chip; and

a transmitter circuit within the chip, the transmitter circuit being coupled to the processor to accept a digital input signal including a plurality of digital values from the processor, the transmitter circuit being operable to send an output signal including a series of signal levels representing the digital values and to emphasize high frequency components of the output signal relative to low frequency components of the output signal.

2. The component as claimed in claim 1 wherein the transmitter circuit is operable to send the output signal with an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz.

3. The component as claimed in claim 1 wherein the processor is a CPU.

4. The component as claimed in claim 1 wherein the transmitter circuit is operable to emphasize signal levels representing values following transitions between values relative to signal levels representing repeated values.

5. The component as claimed in claim 1 wherein the chip has I/O connections and the transmitter circuit is coupled to one or more of the I/O connections to send the output signal through the one or more I/O connections.

6. The component as claimed in claim 5 wherein the transmitter circuit is operable to send the output signal in nonmodulated form.

7. The component as claimed in claim 5 wherein the transmitter circuit is operable to send the signal levels as currents.

8. The component as claimed in claim 7 wherein the transmitter circuit is operable to send the signal levels as opposite currents through a pair of I/O connections.

9. The component as claimed in claim 1 wherein each digital value is represented by one of the signal levels in the output signal.

10. The component as claimed in claim 1 wherein the digital input signal includes a plurality of bits and each bit of the digital input signal is represented by one of the signal levels in the output signal.

11. The component as claimed in claim 1 further comprising at least one additional transmitter circuit within the chip, each additional transmitter circuit being coupled to the processor and operable to accept an additional digital input signal from the processor and send an additional output signal representing such additional input signal.

12. The component as claimed in claim 11 wherein the chip has I/O connections and the transmitter circuits are coupled to a plurality of the I/O connections and operable to send the output signals through the I/O connections.

13. The component as claimed in claim 111 wherein the transmitter circuits are operable to provide output signals representing a parallel stream of data from the processor.

14. A component comprising:

a semiconductor chip;

a hub within the chip, the hub being operable to accept and send data; and

a plurality of transmitter circuits within the chip, each of the transmitter circuits being coupled to the hub to accept a digital input signal including a plurality of digital values from the from the hub, each of the transmitter circuits being operable to send an output signal including a series of signal levels representing the digital values accepted by that transmitter circuit and to emphasize high frequency components of the output signal relative to low frequency components of the output signal.

15. The component as claimed in claim 14 wherein each of the transmitter circuits is operable to send the output signal from that transmitter circuit with an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz.

16. The component as claimed in claim 14 wherein each of the transmitter circuits is operable to emphasize signal levels representing values following transitions between values relative to signal levels representing repeated values.

17. The component as claimed in claim 14 wherein the chip has I/O connections and each of the transmitter circuits is coupled to one or more of the I/O connections to send the output signal through the one or more I/O connections.

18. The component as claimed in claim 17 wherein the transmitter circuits are operable to send the output signals in nonmodulated form.

19. The component as claimed in claim 17 wherein the transmitter circuits are operable to send the signal levels as currents.

20. The component as claimed in claim 19 wherein each transmitter circuit is operable to send the signal levels of the output signal from that transmitter circuit as opposite currents through a pair of I/O connections.

21. The component as claimed in claim 14 wherein each digital value is represented by one of the signal levels in one of the output signals.

22. The component as claimed in claim 14 wherein each digital input signal includes a plurality of bits and each bit of each digital input signal is represented by one of the signal levels in one of the output signals.

23. The component as claimed in claim 14 wherein the transmitter circuits are operable to provide output signals representing a parallel stream of data from the hub.