PVT drift compensation

• US 20060294410A1
• Filed: 06/22/2005
• Published: 12/28/2006
• Est. Priority Date: 06/22/2005
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Kizer, Jade, Doriswamy, Sivakumar
• Granted Patent: US 7,519,844 B2
• Time in Patent Office: Days
• US Class Current: 713/500
• CPC Class Codes: H03L 1/022 by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature H03L1/021 takes precedence
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H04L 7/0079 Receiver details

Abstract

A timing circuit for generating a timing signal having a predetermined relationship with a reference signal. The timing circuit includes a locked loop for generating the recovered clock signal, comparing the phase of the reference signal to the phase of the timing signal, and adjusting the phase of the timing signal based on the comparison; and a PVT (Process-Voltage-Temperature) line operatively associated with the locked loop so that PVT drift in the PVT line counters PVT drift in the locked loop.

Claims

1. A timing circuit for generating a timing signal having a predetermined relationship with a reference signal, comprising:

a locked loop for generating the timing signal, comparing the phase of the reference signal to the phase of the timing signal, and adjusting the phase of the timing signal based on such comparison; and

a PVT (Process-Voltage-Temperature) line operatively associated with the locked loop so that PVT drift in the PVT line counters PVT drift in the locked loop.

2. The timing circuit as claimed in claim 1, wherein the PVT line is within a feedback path of the locked loop.

3. The timing circuit as claimed in claim 1, wherein the reference signal passes through the PVT line before being received by the locked loop.

4. The timing circuit as claimed in claim 1, wherein the PVT line is within a tracking loop that tracks PVT drift of the PVT line.

5. The timing circuit as claimed in claim 1, wherein the PVT line is coupled to the output of the locked loop.

6. The timing circuit as recited in claim 1, wherein the PVT line is adjustable.

7. The timing circuit as recited in claim 6, wherein the PVT line is adjustable according to a digital code.

8. The timing circuit as claimed in claim 1, wherein the PVT line comprises a first adjustable PVT line and a second adjustable PVT line.

9. The timing circuit as claimed in claim 8, wherein the first and second adjustable PVT lines are adjustable according to a digital code.

10. The timing circuit as claimed in claim 1, wherein the PVT line comprises a plurality of inverters.

11. A clock recovery circuit for generating a recovered clock signal having a predetermined relationship with an incoming signal, comprising:

means for generating the recovered clock signal, comparing the phase of the incoming signal to the phase of the recovered clock signal, and adjusting the phase of the recovered clock signal based on such comparison; and

PVT (Process-Voltage-Temperature) drift means operatively associated with the means for generating so that PVT drift in the PVT drift means counters PVT drift in the means for generating.

12. The clock recovery circuit as claimed in claim 11, wherein the PVT drift means is within a feedback path of means for generating.

13. The clock recovery circuit as claimed in claim 11, wherein the incoming signal passes through the PVT drift means before being received by the means for generating.

14. The clock recovery circuit as claimed in claim 11, wherein the PVT drift means is within a tracking loop that tracks PVT drift of the PVT drift means.

15. The clock recovery circuit as claimed in claim 11, wherein the PVT drift means is coupled to an output of the means for generating.

16. The clock recovery circuit as recited in claim 11, wherein the PVT drift means is adjustable.

17. The clock recovery circuit as recited in claim 16, wherein the PVT drift means is adjustable according to a digital code.

18. The clock recovery circuit as claimed in claim 11, wherein the PVT drift means comprises a first adjustable PVT line and a second adjustable PVT line.

19. The clock recovery circuit as claimed in claim 18, wherein the first and second adjustable PVT lines are adjustable according to a digital code.

20. The clock recovery circuit as claimed in claim 11, wherein the PVT drift means comprises a plurality of inverters.

21. An information-bearing medium having computer-readable information thereon, the computer-readable information being configured to actuate a circuit-forming apparatus to form a cell of an integrated circuit including a clock recovery circuit, the clock recovery circuit being operable to generate a recovered clock signal having a predetermined relationship with an incoming signal, the clock recovery circuit comprising:

at least one locked loop for generating the recovered clock signal, comparing the phase of the incoming signal to the phase of the recovered clock signal, and adjusting the phase of the recovered clock signal based on such comparison; and

at least one PVT (Process-Voltage-Temperature) line operatively associated with the locked loop so that PVT drift in the PVT line counters PVT drift in the locked loop.

22. The clock recovery circuit as claimed in claim 21, wherein the PVT line is within a feedback path of the locked loop.

23. The clock recovery circuit as claimed in claim 21, wherein the incoming signal passes through the PVT line before being received by the locked loop.

24. The clock recovery circuit as claimed in claim 21, wherein the PVT line is within a tracking loop that tracks PVT drift of the PVT line.

25. The clock recovery circuit as claimed in claim 21, wherein the PVT line is coupled to the output of the locked loop.

26. The clock recovery circuit as recited in claim 21, wherein the PVT line is adjustable.

27. The clock recovery circuit as recited in claim 26, wherein the PVT line is adjustable according to a digital code.

28. The clock recovery circuit as claimed in claim 21, wherein the at least one PVT line comprises a first adjustable PVT line and a second adjustable PVT line.

29. The clock recovery circuit as claimed in claim 28, wherein the first and second adjustable PVT lines are adjustable according to a digital code.

30. The clock recovery circuit as claimed in claim 21, wherein the PVT line comprises a plurality of inverters.

31. A method of generating a recovered clock signal having a predetermined relationship with an incoming signal, the method comprising the steps of:

generating the recovered clock signal;

comparing the phase of the incoming signal to the phase of the recovered clock signal;

adjusting the phase of the recovered clock signal based on the comparing; and

compensating for PVT drift associated with the recovered clock signal with a PVT line.