Method for producing a vertical field effect transistor

• US 20070004149A1
• Filed: 04/28/2006
• Published: 01/04/2007
• Est. Priority Date: 10/30/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tews, Helmut
• Granted Patent: US 7,405,127 B2
• Time in Patent Office: Days
• US Class Current: 438/268
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility.

Claims

1. A method for producing a vertical field effect transistor comprising the following steps:

forming of at least one structure on a substrate which serves for forming the channel region of a field effect transistor;

applying an electrically insulating spacer layer near to the substrate after the formation of the structure;

applying an electrically conductive or semiconducting control electrode layer which serves for forming the control electrode of the field effect transistor planarization of the control electrode layer; and

whole-area etching-back of the planarized control electrode layer.

2. The method of claim 1, further comprising uncovering during the etching-back of the planarized control electrode layer a part of the structure or a part of an insulating layer covering the structure.

3. The method as claimed in claim 1, further comprising, prior to applying the control layer electrode, the steps of:

planarizing the spacer layer near to the substrate; and

whole-area etching-back of the spacer layer near to the substrate.

4. The method of claim 1 further comprising:

applying an electrically insulating spacer layer remote from the substrate after the etching-back of the control electrode layer;

planarizing the spacer layer remote from the substrate; and

whole-area etching-back of the spacer layer remote from the substrate.

5. The method of claim 4, further comprising, after the application of the spacer layer remote from the substrate, the steps of:

applying a connection electrode layer serving for forming a connection electrode of the field effect transistor; and

planarizing the connection electrode layer.

6. The method of claim 5, further comprising joint patterning of the control electrode layer and of the spacer layer remote from the substrate.

7. The method of claim 1, further comprising forming an electrically insulating layer on a part of the structure near the substrate after the etching-back of the spacer layer and prior to the application of the control electrode layer.

8. The method of claim 7, wherein the electrically insulating layer is produced by whole-area layer deposition or by thermal growth.

9. The method of claim 1, further comprising forming the structure with the aid of a hard mask.

10. The method of claim 1, further comprising:

applying a charge storage layer near to the substrate after the application of the spacer layer and prior to the application of the control electrode layer;

patterning the charge storage layer prior to the application of the control electrode layer.

11. The method of claim 10, further comprising:

planarizing the charge storage layer;

whole-area etching-back of the charge storage layer;

forming at least one spacer element on the structure,

patterning the charge storage layer using the spacer element.

12. A vertical field effect transistor comprising a projection formed on a substrate for forming a channel region of a field effect transistor;

a control electrode region of a control electrode of the field effect transistor formed on mutually opposite sides of the projection;

an insulating region arranged between the control electrode regions and the projection electrically insulating and adjoining the channel region;

a first connection region near the substrate at one end of the channel region; and

a second connection region remote from the substrate at the other end of the channel region, the control electrode having a planar interface which lies parallel to a base area of the projection near the substrate.

13. The field effect transistor of claim 12, wherein the control electrode is delimited by the planar interface in at least ninety percent of its region in the direction of a normal (N) to the base area, away from the substrate.

14. The field effect transistor of claim 12, further comprising at least one charge storage region arranged between an insulating region and a control electrode region.

15. The field effect transistor of claim 14, which the charge storage region is contained in a charge storage material having a further planar interface remote from the substrate, said further planar interface lying parallel to the base area of the projection.

16. The field effect transistor of claim 15, wherein the charge storage material is delimited by the further planar interface remote from the substrate at least ninety percent of its region in the direction of the normal (N) to the base area, away from the substrate.

17. The field effect transistor as claimed in claim 12, wherein the control electrode encloses the projection along a closed circulation, or in the charge storage material encloses the projection along a closed circulation.

18. The field effect transistor as claimed in claim 12, wherein:

the projection and the substrate are formed in monocrystalline fashion;

the insulating region is a region grown on the projection;

the connection region near to the substrate is arranged with a lateral offset with respect to the base area;

or

the projection has a minimal dimensioning of less than one hundred nanometers.