Method and system for transmiting N-bit video data over a serial link

• US 20070009060A1
• Filed: 06/24/2005
• Published: 01/11/2007
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Wolf, Paul, Lavelle, Michael
• Granted Patent: US 7,599,439 B2
• Time in Patent Office: Days
• US Class Current: 375/295
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N≠K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.

Claims

1. A transmitter for transmitting N-bit video over a serial link configured to transmit encoded K-bit words of video data, said transmitter comprising:

a subsystem operable in at least one N-bit mode to pack a sequence of N-bit words of video data into a sequence of fragments, where N≠

K and each of the fragments consists of K bits of the video data; and

circuitry coupled to the subsystem and having at least one output configured to be coupled to the serial link, wherein the circuitry is configured to generate a sequence of encoded fragments by encoding each fragment in the sequence of fragments and to assert the sequence of encoded fragments to the at least one output, whereby the encoded fragments can be transmitted over the link when said link is coupled to the at least one output.

2. The transmitter of claim 1, wherein the sequence of encoded fragments is a sequence of groups of M encoded fragments, where M=N/D, D is the greatest common divisor of N and K, the N-bit words of video data are asserted to the subsystem at a first rate equal to P of the N-bit words per unit time, and the circuitry is configured to assert the sequence of encoded fragments to the at least one output at a second rate that is at least substantially equal to (N/K)P of the encoded fragments per unit time.

3. The transmitter of claim 2, wherein the transmitter is configured to execute state sequences, each consisting of M states, during operation in each said N-bit mode, said state sequences including:

active video interval sequences, wherein M of the encoded fragments are asserted to the at least one output during each of the active video interval sequences;

blanking interval sequences, wherein M blanking characters is asserted to the at least one output during each of the blanking interval sequences, and one of said M blanking characters is identical to another one of said M blanking characters;

active video to blanking transitional sequences, wherein one of the encoded fragments is asserted to the at least one output during a first state of each of the active video to blanking transitional sequences and a last state of each of the active video to blanking transitional sequences occurs in a blanking interval; and

blanking to active video transitional sequences, wherein one of the encoded fragments is asserted to the at least one output during a last state of each of the blanking to active video transitional sequences and a first state of each of the blanking to active video transitional sequences occurs in a blanking interval,

wherein the transmitter is configured to assert the sequence of encoded fragments to the at least one output without omitting assertion of any encoded fragment thereof by executing, completely or partially, a sufficient number of state sequence cycles, each of the state sequence cycles including any number of the active video interval sequences, followed by one of the active video to blanking transitional sequences, followed by a number of the blanking interval sequences, followed by one of the blanking to active video transitional sequences.

4. The transmitter of claim 1, wherein the sequence of encoded fragments is a sequence of groups of M encoded fragments, each of the M encoded fragments in each of the groups has a different phase within the group, and the transmitter is configured to assert the encoded fragments to the at least one output during active video intervals and to assert packing phase data to the at least one output during at least some blanking intervals between the active video intervals, wherein the packing phase data indicate the phase of one of the encoded fragments that has been asserted to the at least one output at a known checkpoint.

5. The transmitter of claim 4, wherein the packing phase data asserted during a blanking interval indicate the phase of the last one of the encoded fragments asserted to the at least one output before said blanking interval.

6. The transmitter of claim 5, wherein the circuitry includes encoder circuitry having a first pair of outputs configured to be coupled to a data channel of a transition minimized differential signaling (TMDS) link and a second pair of outputs configured to be coupled to a second data channel of the TMDS link, the encoder circuitry is configured to receive and encode control bits and to assert code words indicative of the encoded control bits to the first pair of outputs and the second pair of outputs, and the transmitter is operable in a message mode in which control bits including packing phase bits are asserted to the encoder circuitry and the encoder circuitry asserts code words indicative of the packing phase bits to the first pair of outputs and the second pair of outputs, wherein said code words indicative of the packing phase bits determine the packing phase data.

7. The transmitter of claim 6, wherein the transmitter is also operable in a second mode in which a sequence of four-bit control words are asserted to the encoder circuitry, each of said control words including a CTL0 bit, a CTL1 bit, a CTL2 bit, and a CTL3 bit, and wherein the control bits asserted to the encoder circuitry in the message mode include a sequence of message mode control words, each of said message mode control words including a CTL0 bit, two of the packing phase bits, and a CTL3 bit.

8. The transmitter of claim 6, wherein K=8, the transmitter is also operable in an 8-bit mode in which the circuitry asserts 10-bit TMDS code words indicative of 8-bit words of the video data to the at least one output during active video intervals at a rate of one 10-bit TMDS code word per cycle of a link clock having frequency P, each of the encoded fragments is a 10-bit TMDS code word, the transmitter is also operable in each said N-bit mode to assert the sequence of encoded fragments to the at least one output during active video intervals at a rate of one encoded fragment per cycle of a second link clock having frequency at least substantially equal to (N/8)P, and the packing phase data are indicated by a sequence of 10-bit TMDS code words asserted to the first pair of outputs and the second pair of outputs during the first X cycles of the second link clock during at least one blanking interval between active video intervals during operation of the transmitter in each said N-bit mode, where X is a predetermined integer.

9. The transmitter of claim 5, wherein the transmitter is configured to assert the encoded fragments to the at least one output during active video intervals and to assert packets including encoded auxiliary data to the at least one output during data islands, wherein each of the data islands is a time interval that neither coincides with nor overlaps any of the active video intervals, the transmitter is also configured to assert control data to the at least one output during control data periods, wherein the control data periods neither coincide with nor overlap any of the data islands and neither coincide with nor overlap any of the active video intervals, and at least one of the packets includes the packing phase data.

10. The transmitter of claim 5, wherein the transmitter is configured to assert color mode data to the at least one output during at least some blanking intervals between active video intervals, wherein the color mode data are indicative of the N-bit mode in which the subsystem is operating.

11. The transmitter of claim 10, wherein the circuitry includes encoder circuitry having a first pair of outputs configured to be coupled to a data channel of a transition minimized differential signaling (TMDS) link and a second pair of outputs configured to be coupled to a second data channel of the TMDS link, the encoder circuitry is configured to receive and encode control bits and to assert code words indicative of the encoded control bits to the first pair of outputs and the second pair of outputs, and the transmitter is operable in a first message mode in which control bits including color mode bits are asserted to the encoder circuitry and the encoder circuitry asserts code words indicative of the color mode bits to the first pair of outputs and the second pair of outputs, wherein said code words indicative of the color mode bits determine the color mode data.

12. The transmitter of claim 11, wherein the transmitter is also operable in a second message mode in which a sequence of second message mode control words are asserted to the encoder circuitry, each of said second message mode control words including a CTL0 bit, a pair of packing phase bits, and a CTL3 bit, and the encoder circuitry asserts code words indicative of the packing phase bits to the first pair of outputs and the second pair of outputs, wherein said code words indicative of the packing phase bits determine the packing phase data, and wherein the control bits asserted to the encoder circuitry in the first message mode include a sequence of four-bit words, each including a CTL0 bit, a pair of the color mode bits, and a CTL3 bit.

13. The transmitter of claim 10, wherein the transmitter is configured to assert the encoded fragments to the at least one output during active video intervals and to assert packets including encoded auxiliary data to the at least one output during data islands, wherein each of the data islands is a time interval that neither coincides with nor overlaps any of the active video intervals, the transmitter is also configured to assert control data to the at least one output during control data periods, wherein the control data periods neither coincide with nor overlap any of the data islands and neither coincide with nor overlap any of the active video intervals, and at least one of the packets includes the color mode data.

14. The transmitter of claim 1, wherein K=8, the transmitter is also operable in an 8-bit mode in which the circuitry asserts Q-bit code words indicative of 8-bit words of the video data to the at least one output during active video intervals at a rate of one Q-bit word per cycle of a link clock having frequency P.

15. The transmitter of claim 14, wherein each of the encoded fragments is a Q-bit code word, and the transmitter is also operable in each said N-bit mode to assert the sequence of encoded fragments to the at least one output during active video intervals at a rate of one encoded fragment per cycle of a second link clock having frequency at least substantially equal to (N/8)P.

16. The transmitter of claim 15, wherein the serial link is a transition minimized differential signaling (TMDS) link and the circuitry is configured to generate a the sequence of encoded fragments by encoding the fragments as 10-bit TMDS code words.

17. The transmitter of claim 15, wherein the transmitter is operable in a 10-bit mode in which N=10, the sequence of encoded fragments is a sequence of groups, each said group consists of five of the encoded fragments, and each encoded fragment in each said group has a different phase within the group.

18. The transmitter of claim 17, wherein the subsystem is configured to operate as follows when the transmitter operating in the 10-bit mode enters a blanking interval after asserting a Q-bit code word indicative of a second fragment of a group to the at least one output but before asserting a Q-bit code word indicative of a third fragment of the group to the at least one output:

during a first cycle of the second link clock in the blanking interval, the subsystem enters a first intermediate state;

during a second cycle of the second link clock in the blanking interval, the subsystem enters a second intermediate state;

during a third cycle of the second link clock in the blanking interval, the subsystem enters a third intermediate state;

during a fourth cycle of the second link clock in the blanking interval, the subsystem enters a first blanking state; and

during subsequent cycles of the second link clock in the blanking interval, the subsystem enters a repeating sequence of a second blanking state, a third blanking state, a fourth blanking state, a fifth blanking state, and the first blanking state.

19. The transmitter of claim 18, wherein the subsystem is configured to operate as follows when the transmitter operating in the 10-bit mode enters a blanking interval after asserting a Q-bit code word indicative of a third fragment of a group to the at least one output but before asserting a Q-bit code word indicative of a fourth fragment of the group to the at least one output:

during a first cycle of the second link clock in the blanking interval, the subsystem enters the second intermediate state;

during a second cycle of the second link clock in the blanking interval, the subsystem enters the third intermediate state;

during a third cycle of the second link clock in the blanking interval, the subsystem enters the first blanking state;

during a fourth cycle of the second link clock in the blanking interval, the subsystem enters the second blanking state; and

during subsequent cycles of the second link clock in the blanking interval, the subsystem enters a repeating sequence of the third blanking state, the fourth blanking state, the fifth blanking state, the first blanking state, and the second blanking state.

20. The transmitter of claim 19, wherein the subsystem is configured to operate as follows when the transmitter operating in the 10-bit mode enters a blanking interval after asserting a Q-bit code word indicative of a fourth fragment of a group to the at least one output but before asserting a Q-bit code word indicative of a fifth fragment of the group to the at least one output:

during a first cycle of the second link clock in the blanking interval, the subsystem enters the third intermediate state;

during a second cycle of the second link clock in the blanking interval, the subsystem enters the first blanking state;

during a third cycle of the second link clock in the blanking interval, the subsystem enters the second blanking state;

during a fourth cycle of the second link clock in the blanking interval, the subsystem enters the third blanking state; and

during subsequent cycles of the second link clock in the blanking interval, the subsystem enters a repeating sequence of the fourth blanking state, the fifth blanking state, the first blanking state, the second blanking state, and the third blanking state.

21. The transmitter of claim 20, wherein the transmitter operating in the 10-bit mode is configured to operate as follows when entering an active video interval:

upon entering the active video interval with the subsystem in the fifth blanking state, the circuitry asserts a Q-bit code word indicative of a first fragment of a group to the at least one output during a first cycle of the second link clock in the active video interval;

upon entering the active video interval with the subsystem in the first blanking state, the circuitry asserts a Q-bit code word indicative of a second fragment of a group to the at least one output during a first cycle of the second link clock in the active video interval;

upon entering the active video interval with the subsystem in the second blanking state, the circuitry asserts a Q-bit code word indicative of a third fragment of a group to the at least one output during a first cycle of the second link clock in the active video interval; and

upon entering the active video interval with the subsystem in the third blanking state, the circuitry asserts a Q-bit code word indicative of a fourth fragment of a group to the at least one output during a first cycle of the second link clock in the active video interval.

22. The transmitter of claim 15, wherein the transmitter is operable in a 12-bit mode in which N=12, the sequence of encoded fragments is a sequence of groups, each said group consists of three of the encoded fragments, and each encoded fragment in each said group has a different phase within the group.

23. The transmitter of claim 22, wherein the subsystem is configured to operate as follows when the transmitter operating in the 12-bit mode enters a blanking interval after asserting a Q-bit code word indicative of a second fragment of a group to the at least one output but before asserting a Q-bit code word indicative of a third fragment of the group to the at least one output:

during a first cycle of the second link clock in the blanking interval, the subsystem enters a third blanking state; and

during subsequent cycles of the second link clock in the blanking interval, the subsystem enters a repeating sequence of a first blanking state, a second blanking state, and the third blanking state.

24. The transmitter of claim 23, wherein the transmitter operating in the 12-bit mode is configured to operate as follows when entering an active video interval with the subsystem in the third blanking state:

during a first cycle of the second link clock in the active video interval, the circuitry asserts a Q-bit code word indicative of a first fragment of a group to the at least one output.

25. The transmitter of claim 15, wherein the transmitter is operable in a 16-bit mode in which N=16, the sequence of encoded fragments is a sequence of groups, each said group consists of two of the encoded fragments, and each encoded fragment in each said group has a different phase within the group.

26. The transmitter of claim 25, wherein the subsystem is configured to operate as follows when the transmitter operating in the 16-bit mode enters a blanking interval after asserting a Q-bit code word indicative of a second fragment of a group to the at least one output but before asserting a Q-bit code word indicative of a first fragment of a subsequent group to the at least one output:

during a first cycle of the second link clock in the blanking interval, the subsystem enters a first blanking state; and

during subsequent cycles of the second link clock in the blanking interval, the subsystem enters a repeating sequence of a second blanking state, and the first blanking state.

27. The transmitter of claim 26, wherein the transmitter operating in the 16-bit mode is configured to operate as follows when entering an active video interval with the subsystem in the second blanking state:

during a first cycle of the second link clock in the active video interval, the circuitry asserts a Q-bit code word indicative of a first fragment of a group to the at least one output.

28. The transmitter of claim 1, wherein the sequence of encoded fragments is a sequence of groups of M encoded fragments, each of the M encoded fragments in each of the groups has a different phase within the group, the circuitry is configured to assert the sequence of encoded fragments to the at least one output during active video intervals and to assert blanking characters to the at least one output during blanking intervals, and the transmitter is configured to execute state machine sequences, each consisting of M states, that implement transitions between the active video intervals and the blanking intervals at boundaries between assertion of different encoded fragments of a single group, and between boundaries that occur between assertion of different groups, without omitting assertion of any encoded fragment in the sequence of encoded fragments.

29. The transmitter of claim 28, wherein M=N/D, where D is the greatest common divisor of N and K, the transmitter is also operable in a K-bit mode in which the circuitry asserts code words indicative of K-bit words of the video data to the at least one output during active video intervals at a rate of one code word per cycle of a link clock having frequency P, the transmitter is also operable in each said N-bit mode to assert the sequence of encoded fragments to the at least one output during active video intervals at a rate of one encoded fragment per cycle of a second link clock having frequency at least substantially equal to (N/K)P.

30. The transmitter of claim 29, wherein the transmitter is configured to assert packing phase data to the at least one output during at least some blanking intervals between the active video intervals, the packing phase data asserted during a blanking interval indicate the phase of the last one of the encoded fragments asserted to the at least one output before said blanking interval.

31. The transmitter of claim 30, wherein the packing phase data are indicated by a sequence of code words asserted to a first pair of outputs of the circuitry and a second pair of outputs of the circuitry during the first X cycles of the second link clock during at least one blanking interval between active video intervals during operation of the transmitter in each said N-bit mode, where X is an integer.

32. The transmitter of claim 1, wherein one said N-bit mode is a mode in which N=L*P, where L and P are integers, and the transmitter is also operable in a P-bit mode in which the video data consist of P-bit color components, and the subsystem in the P-bit mode is configured to pack sets of L consecutive P-bit color components of the video data into N-bit words, and to pack a sequence of the N-bit words into the sequence of fragments in the same manner that the subsystem in the N-bit mode packs a sequence of N-bit words of the video data into the sequence of fragments.

33. The transmitter of claim 1, wherein the sequence of encoded fragments is a sequence of groups of M encoded fragments, each of the M encoded fragments in each of the groups has a different phase within the group, and the transmitter is configured to assert the encoded fragments to the at least one output during active video intervals, and to assert blanking data to the at least one output during blanking intervals between the active video intervals, so as to indicate implicitly the phase of each of the encoded fragments that is asserted to the at least one output at each occurrence of a known checkpoint.

34. The transmitter of claim 33, wherein the phase of said each of the encoded fragments is indicated implicitly by constraining occurrence of the checkpoint so as to fix said phase at each occurrence of the checkpoint.

35. The transmitter of claim 33, wherein the phase of said each of the encoded fragments is indicated implicitly by restarting transmission of one said sequence of groups at each occurrence of the checkpoint.

36. A transmitter, including:

a subsystem operable in any selected one of a number of different 3N-bit pixel modes to pack sequences of N-bit color components of video data into sequences of fragments, where N≠

8, each of the fragments consists of 8 bits of the video data, and the 3N-bit pixel modes include a 30-bit pixel mode, a 36-bit pixel mode, and a 48-bit pixel mode; and

circuitry coupled to the subsystem and having outputs configured to be coupled to a transition minimized differential signaling (TMDS) link, wherein the circuitry is configured to generate sequences of encoded fragments by performing TMDS encoding on the sequences of fragments and to assert the sequences of encoded fragments to the outputs during active video intervals, whereby the encoded fragments can be transmitted over the TMDS link when said TMDS link is coupled to the outputs,

wherein the transmitter is operable in a 24-bit pixel mode in which the subsystem asserts 8-bit components of 24-bit pixels to the circuitry, the circuitry performs TMDS encoding on the 8-bit components to generate a 10-bit TMDS code word in response to each of the 8-bit components, and the circuitry asserts each said TMDS code word to the outputs, and

wherein each of the sequences of fragments is a sequence of M_N-fragment groups, where MN is an integer whose value depends on which of the 3N-bit pixel modes is the selected one of the 3N-bit pixel modes, each of the fragments in each of the groups has a different phase within the group, the circuitry is configured to assert blanking characters to the outputs during blanking intervals, and the transmitter is configured to implement state machine sequences that implement transitions between the active video intervals and the blanking intervals at boundaries between assertion of different encoded fragments of a single one of the groups, and between boundaries that occur between assertion of different ones of the groups, without omitting assertion of any encoded fragment in any of the sequences of encoded fragments.

37. The transmitter of claim 36, wherein the transmitter is also operable in an 18-bit pixel mode in which the video data are 18-bit video data, and the subsystem in the 18-bit pixel mode is configured to pack consecutive 6-bit color components of the video data into 12-bit words, and to pack sequences of the 12-bit words into the sequences of fragments in the same manner that the subsystem in the 36-bit pixel mode packs consecutive 12-bit color components of the video data into sequences of fragments.

38. The transmitter of claim 36, wherein transmitter in the 24-bit pixel mode is configured to assert each said TMDS code word to the outputs at a rate of one said TMDS code word per cycle of a link clock having frequency P, the encoded fragments asserted to the outputs in each said 3N-bit pixel mode are also TMDS code words, and the transmitter in each said 3N-bit pixel mode is configured to assert the TMDS code word to the outputs at a rate of one of the TMDS code words per cycle of a second link clock having frequency at least substantially equal to (N/8)P.

39. A receiver, including:

circuitry having inputs configured to be coupled to a serial link, wherein the circuitry is configured to recover K-bit words of video data that have been transmitted to at least a subset of the inputs; and

a subsystem coupled to the circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠

K, and the subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words.

40. The receiver of claim 39, wherein the sequence of K-bit fragments is a sequence of M-fragment groups, each of the fragments in each of the groups has a different phase within the group, the circuitry is configured to recover the K-bit words of video data during active video intervals and to recover packing phase data that have been transmitted to at least some of the inputs during at least some blanking intervals between the active video intervals, the packing phase data indicate the phase of one of the fragments transmitted at a known checkpoint, and the circuitry is configured to generate at least one control bit in response to the packing phase data and to assert each said control bit to the subsystem to set said subsystem in a state corresponding to said phase of said one of the fragments transmitted at the known checkpoint.

41. The receiver of claim 40, wherein the packing phase data recovered during each blanking interval indicate the phase of the last one of the fragments transmitted before said blanking interval, and the circuitry is configured to generate the at least one control bit in response to the packing phase data and to assert each said control bit to the subsystem to set said subsystem in a state corresponding to said phase of the last one of the fragments transmitted before said blanking interval.

42. The receiver of claim 41, wherein the circuitry is configured to recover color mode data that have been transmitted to at least some of the inputs during at least some blanking intervals between the active video intervals to indicate in which N-bit mode the receiver should operate, and the circuitry is configured to generate at least one control bit in response to the color mode data and to assert each said control bit to the subsystem.

43. The receiver of claim 39, wherein the circuitry is also configured to recover a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, and the circuitry includes a frequency divider coupled to receive the link clock and operable in the N-bit mode to generate a pixel clock having frequency P at least substantially equal to (K/N)L in response to the link clock.

44. The receiver of claim 43, wherein the subsystem includes a FIFO coupled to receive the link clock and the pixel clock, and the subsystem is configured to clock the fragments into the FIFO in response to the link clock and to clock the sequence N-bit video data words out of the FIFO in response to the pixel clock.

45. The receiver of claim 39, wherein the circuitry is configured to recover code words indicative of K-bit words of video data that have been transmitted to at least some of the inputs over the serial link and to decode the code words to recover the K-bit words of video data.

46. The receiver of claim 45, wherein K=8, the link is a transition minimized differential signaling (TMDS) link, the circuitry is configured to recover 10-bit TMDS code words indicative of the 8-bit words of video data and to decode the TMDS code words to recover the 8-bit words of video data.

47. The receiver of claim 45, wherein K=8, the receiver is operable in a 10-bit mode in which N=10, the sequence of 8-bit fragments is a sequence of groups, each said group consists of five of the fragments, each fragment in each said group has a different phase within the group, the circuitry is configured to recover a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, the circuitry is operable in the 10-bit mode to generate a pixel clock having frequency P at least substantially equal to (⅘

)L in response to the link clock, and the receiver operating in the 10-bit mode is configured to operate as follows upon entering a blanking interval after a second fragment of a group has been asserted to the subsystem but before a third fragment of the group has been asserted to the subsystem;

during a first cycle of the link clock in the blanking interval, the receiver enters a first intermediate state;

during a second cycle of the link clock in the blanking interval, the receiver enters a second intermediate state;

during a third cycle of the link clock in the blanking interval, the receiver enters a third intermediate state;

during a fourth cycle of the link clock in the blanking interval, the receiver enters a first blanking state; and

during subsequent cycles of the link clock in the blanking interval, the receiver enters a repeating sequence of a second blanking state, a third blanking state, a fourth blanking state, a fifth blanking state, and the first blanking state.

48. The receiver of claim 47, wherein the receiver operating in the 10-bit mode is configured to operate as follows upon entering a blanking interval after a third fragment of a group has been asserted to the subsystem but before a fourth fragment of the group has been asserted to the subsystem:

during a first cycle of the link clock in the blanking interval, the receiver enters the second intermediate state;

during a second cycle of the link clock in the blanking interval, the receiver enters the third intermediate state;

during a third cycle of the link clock in the blanking interval, the receiver enters the first blanking state;

during a fourth cycle of the link clock in the blanking interval, the receiver enters the second blanking state; and

during subsequent cycles of the link clock in the blanking interval, the receiver enters a repeating sequence of the third blanking state, the fourth blanking state, the fifth blanking state, the first blanking state, and the second blanking state.

49. The receiver of claim 48, wherein the receiver operating in the 10-bit mode is configured to operate as follows upon entering a blanking interval after a fourth fragment of a group has been asserted to the subsystem but before a fifth fragment of the group has been asserted to the subsystem:

during a first cycle of the link clock in the blanking interval, the receiver enters the third intermediate state;

during a second cycle of the link clock in the blanking interval, the receiver enters the first blanking state;

during a third cycle of the link clock in the blanking interval, the receiver enters the second blanking state;

during a fourth cycle of the link clock in the blanking interval, the receiver enters the third blanking state; and

during subsequent cycles of the link clock in the blanking interval, the receiver enters a repeating sequence of the fourth blanking state, the fifth blanking state, the first blanking state, the second blanking state, and the third blanking state.

50. The receiver of claim 45, wherein K=8, the receiver is operable in a 12-bit mode in which N=12, the sequence of 8-bit fragments is a sequence of groups, each said group consists of three of the fragments, each fragment in each said group has a different phase within the group, the circuitry is configured to recover a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, the circuitry is operable in the 12-bit mode to generate a pixel clock having frequency P at least substantially equal to (⅔

)L in response to the link clock, and the receiver operating in the 12-bit mode is configured to operate as follows upon entering a blanking interval after a second fragment of a group has been asserted to the subsystem but before a third fragment of the group has been asserted to the subsystem;

during a first cycle of the link clock in the blanking interval, the receiver enters a third blanking state; and

during subsequent cycles of the link clock in the blanking interval, the receiver enters a repeating sequence of a first blanking state, a second blanking state, and the third blanking state.

51. The receiver of claim 45, wherein K=8, the receiver is operable in a 16-bit mode in which N=16, the sequence of 8-bit fragments is a sequence of groups, each said group consists of two of the fragments, each fragment in each said group has a different phase within the group, the circuitry is configured to recover a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, the circuitry is operable in the 16-bit mode to generate a pixel clock having frequency P at least substantially equal to L/2 in response to the link clock, and the receiver operating in the 16-bit mode is configured to operate as follows upon entering a blanking interval after a second fragment of a group has been asserted to the subsystem but before a first fragment of the group has been asserted to the subsystem:

during a first cycle of the link clock in the blanking interval, the receiver enters a first blanking state; and

during subsequent cycles of the link clock in the blanking interval, the receiver enters a repeating sequence of a second blanking state, and the first blanking state.

52. The receiver of claim 39, wherein the sequence of packed K-bit fragments is a sequence of groups of M fragments, where M=N/D, D is the greatest common divisor of N and K, and the subsystem in each said N-bit mode is configured to execute state sequences, each consisting of M states, during operation in each said N-bit mode, said state sequences including:

active video interval sequences, wherein M of the fragments are recovered during each of the active video interval sequences;

blanking interval sequences, wherein M blanking characters are recovered during each of the blanking interval sequences, and one of said M blanking characters is identical to another one of said M blanking characters;

active video to blanking transitional sequences, wherein one of the fragments is recovered during a first state of each of the active video to blanking transitional sequences and a blanking character is recovered during a last state of each of the active video to blanking transitional sequences; and

blanking to active video transitional sequences, wherein one of the fragments is recovered during a last state of each of the blanking to active video transitional sequences and a blanking character is recovered during a first state of each of the blanking to active video transitional sequences,

wherein the subsystem in each said N-bit mode is configured to recover the sequence of N-bit video data words by executing, completely or partially, a sufficient number of state sequence cycles, each of the state sequence cycles including any number of the active video interval sequences, followed by one of the active video to blanking transitional sequences, followed by a number of the blanking interval sequences, followed by one of the blanking to active video transitional sequences.

53. The receiver of claim 39, wherein the circuitry is also configured to generate a multiphase clock set in response to a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, the multiphase clock set includes X clocks, each of said clocks having a different phase and a frequency at least substantially equal to Y*L, where X and Y are integers, so that the multiphase clock set defines X*Y subdivisions of each period of the link clock, and the circuitry includes a frequency divider coupled to receive at least one clock of the multiphase clock set and operable in the N-bit mode to generate a pixel clock having frequency P at least substantially equal to (K/N)L in response to the at least one clock of the multiphase clock set, wherein the frequency divider is configured to generate a waveform, to generate at least one phase shifted version of the waveform, and to combine the waveform and at least one said phase shifted version of the waveform to generate the pixel clock.

54. A receiver, including:

circuitry having inputs configured to be coupled to a transition minimized differential signaling (TMDS) link, wherein the circuitry is configured to configured to recover TMDS code words indicative of 8-bit words of video data that have been transmitted to at least a subset of the inputs and to decode the code words to recover the 8-bit words of video data; and

a subsystem coupled to the circuitry to receive sequences of the 8-bit words and operable in any selected one of a number of different 3N-bit pixel modes in which N≠

8 and the sequences of the 8-bit words are sequences of packed 8-bit fragments of 3N-bit pixels, wherein the subsystem is operable in each said 3N-bit pixel mode to unpack the fragments to recover a sequence of the 3N-bit pixels, the 3N-bit pixel modes include a 30-bit pixel mode, a 36-bit pixel mode, and a 48-bit pixel mode, the receiver is also operable in a 24-bit pixel mode in which the sequences of the 8-bit words received by the subsystem are sequences of 24-bit pixels, and

the circuitry is also configured to recover a link clock having frequency L that has been transmitted to at least a subset of the inputs over the TMDS link, and the circuitry includes a frequency divider coupled to receive the link clock and operable in each said 3N-bit pixel mode to generate a pixel clock having frequency P at least substantially equal to (8/N)L in response to the link clock.

55. A system, including:

a transmitter;

a receiver; and

a serial link coupled between the transmitter and the receiver, wherein the transmitter comprises;

a subsystem operable in at least one N-bit mode to pack a sequence of N-bit words of video data into a sequence of fragments, where N≠

K and each of the fragments consists of K bits of the video data; and

circuitry coupled to the subsystem and having outputs configured to be coupled to data channels of the serial link, wherein the circuitry is configured to generate a sequence of encoded fragments by encoding the fragments and to assert the sequence of encoded fragments to the outputs to transmit the encoded fragments to the receiver over the link.

56. The system of claim 55, wherein the sequence of encoded fragments is a sequence of groups of M encoded fragments, where M=N/D, D is the greatest common divisor of N and K, the N-bit words of video data are asserted to the subsystem at a first rate equal to P of the N-bit words per unit time, and the circuitry of the transmitter is configured to assert the sequence of encoded fragments to the outputs at a second rate that is at least substantially equal to (N/K)P of the encoded fragments per unit time.

57. The system of claim 56, wherein the transmitter is configured to execute state sequences, each consisting of M states, during operation in each said N-bit mode, said state sequences including:

active video interval sequences, wherein M of the encoded fragments are asserted to the outputs during each of the active video interval sequences;

blanking interval sequences, wherein M blanking characters is asserted to the outputs during each of the blanking interval sequences, and one of said M blanking characters is identical to another one of said M blanking characters;

active video to blanking transitional sequences, wherein one of the encoded fragments is asserted to the outputs during a first state of each of the active video to blanking transitional sequences and a last state of each of the active video to blanking transitional sequences occurs in a blanking interval; and

blanking to active video transitional sequences, wherein one of the encoded fragments is asserted to the outputs during a last state of each of the blanking to active video transitional sequences and a first state of each of the blanking to active video transitional sequences occurs in a blanking interval,

wherein the transmitter is configured to assert the sequence of encoded fragments to the outputs without omitting assertion of any encoded fragment thereof by executing, completely or partially, a sufficient number of state sequence cycles, each of the state sequence cycles including any number of the active video interval sequences, followed by one of the active video to blanking transitional sequences, followed by a number of the blanking interval sequences, followed by one of the blanking to active video transitional sequences.

58. The system of claim 55, wherein the sequence of encoded fragments is a sequence of groups of M encoded fragments, each of the M encoded fragments in each of the groups has a different phase within the group, and the transmitter is configured to assert the encoded fragments to the outputs during active video intervals and to assert packing phase data to at least one of the outputs during at least some blanking intervals between the active video intervals, wherein the packing phase data asserted during a blanking interval indicate the phase of the last one of the encoded fragments asserted to the outputs before said blanking interval.

59. The system of claim 58, wherein the circuitry includes encoder circuitry having a first pair of outputs configured to be coupled to a data channel of a transition minimized differential signaling (TMDS) link and a second pair of outputs configured to be coupled to a second data channel of the TMDS link, the encoder circuitry is configured to receive and encode control bits and to assert code words indicative of the encoded control bits to the first pair of outputs and the second pair of outputs, and the transmitter is operable in a message mode in which control bits including packing phase bits are asserted to the encoder circuitry and the encoder circuitry asserts code words indicative of the packing phase bits to the first pair of outputs and the second pair of outputs, wherein said code words indicative of the packing phase bits determine the packing phase data.

60. The system of claim 59, wherein the transmitter is also operable in a second mode in which a sequence of four-bit control words are asserted to the encoder circuitry, each of said control words including a CTL0 bit, a CTL1 bit, a CTL2 bit, and a CTL3 bit, and wherein the control bits asserted to the encoder circuitry in the message mode include a sequence of message mode control words, each of said message mode control words including a CTL0 bit, two of the packing phase bits, and a CTL3 bit

61. The system of claim 58, wherein the transmitter is configured to assert the encoded fragments to the outputs during active video intervals and to assert packets including encoded auxiliary data to at least a subset of the outputs during data islands, wherein each of the data islands is a time interval that neither coincides with nor overlaps any of the active video intervals, the transmitter is also configured to assert control data to the outputs during control data periods, wherein the control data periods neither coincide with nor overlap any of the data islands and neither coincide with nor overlap any of the active video intervals, and at least one of the packets includes the packing phase data.

62. The system of claim 58, wherein the transmitter is configured to assert color mode data to at least one of the outputs during at least some blanking intervals between active video intervals, wherein the color mode data are indicative of the N-bit mode in which the transmitter'"'"'s subsystem is operating.

63. The system of claim 58, wherein the circuitry includes encoder circuitry having a first pair of outputs configured to be coupled to a data channel of a transition minimized differential signaling (TMDS) link and a second pair of outputs configured to be coupled to a second data channel of the TMDS link, the encoder circuitry is configured to receive and encode control bits and to assert code words indicative of the encoded control bits to the first pair of outputs and the second pair of outputs, and the transmitter is operable in a message mode in which control bits including color mode bits are asserted to the encoder circuitry and the encoder circuitry asserts code words indicative of the color mode bits to the first pair of outputs and the second pair of outputs, wherein said code words indicative of the color mode bits determine the color mode data.

64. The system of claim 56, wherein the sequence of encoded fragments is a sequence of groups of M encoded fragments, each of the M encoded fragments in each of the groups has a different phase within the group, and the transmitter is configured to assert the encoded fragments to the outputs during active video intervals, and to assert blanking data to the outputs during blanking intervals between the active video intervals, so as to indicate implicitly the phase of each of the encoded fragments that is asserted to the outputs at each occurrence of a known checkpoint.

65. The system of claim 55, wherein the receiver includes:

receiver circuitry having inputs coupled to the serial link and configured to recover code words indicative of K-bit words of video data that have been transmitted to at least some of inputs over the serial link and to decode the code words to recover the K-bit words of video data; and

an unpacking subsystem coupled to the receiver circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠

K, and the unpacking subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words.

66. The system of claim 65, wherein K=8, the link is a transition minimized differential signaling (TMDS) link, and the receiver circuitry is configured to recover 10-bit TMDS code words indicative of the 8-bit words of video data and to decode the TMDS code words to recover the 8-bit words of video data.

67. The system of claim 65, wherein the receiver circuitry is also configured to generate a multiphase clock set in response to a link clock having frequency L that has been transmitted to at least one of the inputs over the serial link, the multiphase clock set includes X clocks, each of said clocks having a different phase and a frequency at least substantially equal to Y*L, where X and Y are integers, so that the multiphase clock set defines X*Y subdivisions of each period of the link clock, and the receiver circuitry includes a frequency divider coupled to receive at least one clock of the multiphase clock set and operable in the N-bit mode to generate a pixel clock having frequency P at least substantially equal to (K/N)L in response to the at least one clock of the multiphase clock set, wherein the frequency divider is configured to generate a waveform, to generate at least one phase shifted version of the waveform, and to combine the waveform and at least one said phase shifted version of the waveform to generate the pixel clock.

68. The system of claim 55, also including:

a video source coupled to the transmitter and configured to assert the N-bit words of video data and a pixel clock having frequency P to the transmitter, wherein the transmitter is also operable in each said N-bit mode to assert the sequence of encoded fragments to the outputs during active video intervals at a rate of one encoded fragment per cycle of a link clock having frequency L at least substantially equal to (N/K)P, and the transmitter is also operable in each said N-bit mode to transmit the link clock over a clock channel of the link.

69. The system of claim 68, wherein the receiver includes:

receiver circuitry having inputs coupled to the serial link and configured to recover code words indicative of K-bit words of video data that have been transmitted to at least some of the inputs over the serial link and to decode the code words to recover the K-bit words of video data; and

an unpacking subsystem coupled to the receiver circuitry to receive a sequence of the K-bit words and operable in at least one N-bit mode in which the sequence of the K-bit words is a sequence of packed K-bit fragments of a sequence of N-bit video data words, where N≠

K, and the unpacking subsystem is operable in each said N-bit mode to unpack the fragments to recover the sequence of N-bit video data words, and

wherein the receiver circuitry is also coupled to the clock channel of the link and configured to recover the link clock that has been transmitted over the clock channel, and the receiver circuitry includes a frequency divider coupled to receive the link clock and operable in each said N-bit mode to generate a pixel clock having frequency P substantially equal to (K/N)L in response to the link clock.

70. The system of claim 69, wherein the unpacking subsystem includes a FIFO coupled to receive the link clock and the pixel clock, and the unpacking subsystem is configured to clock the fragments into the FIFO in response to the link clock and to clock the sequence N-bit video data words out of the FIFO in response to the pixel clock.