Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-On Resistance

• US 20070012911A1
• Filed: 09/22/2006
• Published: 01/18/2007
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: RJ Mears LLC (Atomera Incorporated)
• Inventors: Blanchard, Richard
• Granted Patent: US 7,531,829 B2
• Time in Patent Office: Days
• US Class Current: 257/15
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/158 Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A semiconductor device may include a substrate and spaced apart source and drain regions defining a channel region therebetween in the substrate. The substrate may have a plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.

Claims

1. A semiconductor device comprising:

a substrate;

spaced apart source and drain regions defining a channel region therebetween in said substrate;

said substrate having a plurality of spaced apart superlattices in the drain region;

each superlattice comprising a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions.

2. The semiconductor device of claim 1 wherein said plurality of spaced apart superlattices also extend into the channel region.

3. The semiconductor device of claim 1 wherein said source and drain regions are laterally spaced apart.

4. The semiconductor device of claim 1 wherein said source and drain regions are vertically spaced apart.

5. The semiconductor device of claim 1 wherein said spaced apart superlattices extend laterally between said source and drain regions.

6. The semiconductor device of claim 1 wherein said spaced apart superlattices extend vertically between said source and drain regions.

7. The semiconductor device of claim 1 wherein said spaced apart superlattices are substantially parallel to one another.

8. The semiconductor device of claim 1 further comprising a gate dielectric layer adjacent the channel region, and a gate electrode layer adjacent said gate dielectric layer.

9. The semiconductor device of claim 1 wherein said base semiconductor portions comprise silicon, and wherein said at least one non-semiconductor monolayer comprises oxygen.

10. The semiconductor device of claim 1 wherein each non-semiconductor layer is a single monolayer thick.

11. The semiconductor device of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.

12. The semiconductor device of claim 1 wherein each superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

13. The semiconductor device of claim 1 wherein all of the base semiconductor portions are the same number of monolayers thick.

14. The semiconductor device of claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

15. The semiconductor device of claim 1 wherein all of the base semiconductor portions are a different number of monolayers thick.

16. The semiconductor device of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

17. The semiconductor device of claim 1 wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

18. The semiconductor device of claim 1 wherein opposing base semiconductor portions in adjacent groups of layers of each superlattice are chemically bound together.

19. A semiconductor device comprising:

a substrate;

spaced apart source and drain regions defining a channel region therebetween in said substrate;

said substrate having a plurality of spaced apart superlattices in the channel region; and

each superlattice comprising a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions.

20. The semiconductor device of claim 19 wherein said source and drain regions are laterally spaced apart.

21. The semiconductor device of claim 19 wherein said source and drain regions are vertically spaced apart.

22. The semiconductor device of claim 19 wherein said spaced apart superlattices extend laterally between said source and drain regions.

23. The semiconductor device of claim 19 wherein said spaced apart superlattices extend vertically between said source and drain regions.

24. The semiconductor device of claim 19 wherein said spaced apart superlattices are substantially parallel to one another.

25. The semiconductor device of claim 19 further comprising a gate dielectric layer adjacent the channel region, and a gate electrode layer adjacent said gate dielectric layer.

26. The semiconductor device of claim 19 wherein said base semiconductor portions comprise silicon, and wherein said at least one non-semiconductor monolayer comprises oxygen.

27. The semiconductor device of claim 19 wherein opposing base semiconductor portions in adjacent groups of layers of each superlattice are chemically bound together.