DRAM INCLUDING A VERTICAL SURROUND GATE TRANSISTOR

• US 20070018223A1
• Filed: 07/31/2006
• Published: 01/25/2007
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Abbott, Todd
• Granted Patent: US 7,566,620 B2
• Time in Patent Office: Days
• US Class Current: 257/303
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.

Claims

1. A method of forming a 4F² area stacked capacitor memory cell, the method comprising:

forming a memory cell comprising a source, a drain, a polysilicon surround gate, and a channel region;

depositing a thin metal on exposed surfaces of at least the polysilicon surround gate; and

exposing the thin metal to heat that is sufficiently high to react the thin metal with a portion of the polysilicon gate in order to form a silicided gate adjacent the polysilicon surround gate.

2. The method of claim 1, wherein the thin metal comprises Cobalt.

3. The method of claim 1, wherein the thin metal comprises Nickel.

4. The method of claim 1, wherein the thin metal comprises Titanium.

5. The method of claim 1, wherein the thin metal comprises a layer of either Cobalt or Nickel and a layer of either Titanium or Titanium Nitride.

6. The method of claim 1, further comprising siliciding at least a portion of the drain to form a silicided drain contact.

7. The method of claim 6, wherein the silicided drain contact comprises a bit line contact.

8. The method of claim 1, wherein the polysilicon surround gate comprises a word line contact.

9. The method of claim 1, wherein the memory cell comprises a DRAM cell.

10. The method of claim 1, further comprising forming a capacitor in contact with the source.

11. A 4F² area stacked capacitor memory cell comprising:

a source region;

a drain region;

a polysilicon surround gate;

a channel region; and

a silicided surround gate adjacent the polysilicon surround gate.

12. The memory cell of claim 11, further comprising a silicided drain contact.

13. A method of forming a memory device comprising a plurality of 4F² area stacked capacitor memory cells, the method comprising:

forming a plurality of memory cells each comprising a source, a drain, a polysilicon surround gate, and a channel region;

depositing a thin metal on exposed surfaces of at least the polysilicon surround gate of each memory cell; and

exposing the thin metal to heat that is sufficiently high to react the thin metal with a portion of the polysilicon gate in order to form a silicided gate adjacent the polysilicon surround gate in each of the memory cells.

14. The method of claim 13, further comprising siliciding at least a portion of the drains of each memory cells in order to form silicided drain contacts in each memory cell.

15. The method of claim 14, wherein a bit line of the memory device comprises a first subset of the silicided drain contacts.

16. The method of claim 13, wherein a word line of the memory device comprises a second subset of the polysilicon surround gates.

17. The method of claim 13, wherein the thin metal comprises material selected from the group comprising Tungsten, Nickel, and Cobalt.

18. The method of claim 13, further comprising depositing a second thin metal on the thin metal prior to exposing the thin metal to heat.

19. The method of claim 18, wherein the second thin metal comprises material selected from the group comprising Titanium and Titanium Nitride.

20. The method of claim 13, wherein the memory device comprises a DRAM.