Method to engineer etch profiles in Si substrate for advanced semiconductor devices

• US 20070020861A1
• Filed: 07/16/2005
• Published: 01/25/2007
• Est. Priority Date: 07/16/2005
• Status: Active Grant

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC), Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Panda, Siddhartha, Greene, Brian, Chong, Yung, Rovedo, Nivo
• Granted Patent: US 7,442,618 B2
• Time in Patent Office: Days
• US Class Current: 438/296
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.

Claims

1. A method of fabrication of an inverted keyhole shaped trench in a semiconductor device;

comprising the steps of;

forming an inverted keyhole shaped trench in said substrate in said first opening using a two step etch comprising;

in a first etch step, etching the substrate using an anisotropic etch to form an upper trench having first sidewalls;

in a second etch step, etching the substrate using an isotropic etch through the upper trench to form a rounded lower trench;

the upper trench and the rounded lower trench form a inverted keyhole trench.

2. The method of claim 1 wherein the first sidewalls have an angle from vertical between 0 and 60 degrees and the anisotropic etch forms a passivation layer on the slanted sidewalls;

and the passivation layer is etch resistant to the isotropic etch;

the substrate is comprised of crystalline Si, SOI or SiGe.

3. The method of claim 1 wherein the first sidewalls have an angle from vertical between 5 and 30 degrees and

the anisotropic etch forms a passivation layer on the slanted sidewalls;

and the passivation layer is etch resistant to the isotropic etch.

4. The method of claim 1 which further includes filling the inverted keyhole trench with a material that insulates and creates compressive or tensile stress on the sidewalls of the inverted keyhole trench.

5. The method of claim 1 which further includes forming a FET device having a channel region in said substrate;

and

filling the inverted keyhole trench with an material that insulates and creates compressive or tensile stress on the channel region.

6. The method of claim 1 which further includes forming a FET device having gate structure and a channel region in said substrate;

and

forming a plurality of inverted keyhole shaped trenches adjacent to the gate structure;

filling inverted keyhole shaped trenches with a stress creating material to form stressor regions;

forming source and drain regions at least partially in the stressor regions.

7. The method of claim 1 which further includes:

forming an etch mask film over a substrate;

forming a first opening through the etch mask film to expose the substrate surface;

etching through the etch mask film to expose the substrate surface;

removing the resist layer;

forming the inverted keyhole shaped trench in said first opening;

said first etch step and said second etch step are in situ.

8. The method of claim 1 wherein said keyhole shaped trench is comprised of an upper trench having vertical or slanted sidewalls and a lower rounded trench.

9. The method of claim 1 which further includes prior to the first etch step, performing a breakthrough etch to remove any native oxide on the surface of the substrate.

10. A method of fabrication of an inverted keyhole trench in a semiconductor device;

comprising the steps of;

forming an inverted keyhole shaped trench in said substrate;

the inverted keyhole shaped trench is comprised of a upper trench with essentially straight sidewalls and a rounded lower trench;

at least partially filling the inverted keyhole shaped trench with a material to create stress on the sidewalls of the inverted keyhole shaped trench to form a stress region.

11. The method of claim 10 wherein the inverted keyhole shaped trench is formed using a two step etch comprising:

in a first etch step, etching the substrate using an anisotropic etch to form an upper trench having first sidewalls;

in a second etch step, etching the substrate using an isotropic etch through the upper trench to form a rounded lower trench;

the upper trench and the rounded lower trench form a inverted keyhole trench.

12. The method of claim 10 wherein the inverted keyhole shaped trench is filled with an dielectric material.

13. The method of claim 10 wherein the inverted keyhole shaped trench is filled with a semiconductor material.

14. The method of claim 10 which further includes forming a FET device having a channel region in said substrate;

and

filling the inverted keyhole shaped trench with a material that insulates and creates compressive or tensile stress on the channel region.

15. The method of claim 10 which further includes forming a FET device having gate structure and a channel region in said substrate;

and forming said inverted keyhole shaped trench adjacent to the gate structure;

filling inverted keyhole shaped trench with a stress creating semiconductor material;

forming source and drain regions at least partially in the stress creating semiconductor material.

16. A method for forming keyhole stressor regions in a semiconductor device comprising the steps of:

a) providing a gate structure over a substrate and isolation regions in said substrate spaced from said gate structure;

b) forming an inverted keyhole shaped trenches adjacent to said isolation regions and said gate structure using the isolation regions and gate structure as an etch mask;

c) filling said inverted keyhole shaped trenches with a stress material to form stressor regions;

the stressor regions create stress in the substrate under the gate structure.

17. The method of claim 16 which further comprises forming source and drain regions at least partially in said stressor regions.

18. The method of claim 16 which further comprises forming source and drain regions at least partially in said stressor region and in said substrate adjacent said gate structure;

the source and drain regions are formed using an implant process.

19. The method of claim 16 which further comprises forming source and drain regions at least partially in said stressor regions and in said substrate adjacent said gate structure;

the source and drain regions are formed doping the stress material.

20. The method of claim 16 wherein said keyhole shaped trench is comprised of an upper trench having vertical or slanted sidewalls and a lower rounded trench.

21. The method of claim 16 wherein the inverted keyhole shaped trenches are formed using a two step etch comprising:

(1) in a first etch step, etching the substrate using an anisotropic etch to form upper trenches having first sidewalls;

(2) in a second etch step, etching the substrate using an isotropic dry etch to form a rounded lower trench;

the upper trench and the rounded lower trench form inverted keyhole trenches.

22. A semiconductor device having stress creating regions comprising:

a gate structure over a substrate;

stress regions in inverted keyhole shaped trenches on opposite sides of said gate structure;

the stress region creates stress in the substrate under the gate structure.

23. The semiconductor device of claim 22 which further comprises:

the stress region are isolation regions in said substrate spaced from said gate structure;

source and drain regions are adjacent to said gate structure.

24. The semiconductor device of claim 22 which further comprises:

isolation regions in said substrate spaced from said gate structure;

the stress regions are stressor regions that are comprised of a semiconductor material;

the source and drain regions are adjacent to said gate structure;

source and drain region are at least partially in said stressor regions.

25. The semiconductor device of claim 22 which further comprises:

isolation regions in said substrate spaced from said gate structure;

the stress regions are stressor regions that are comprised of an semiconductor material selected from the group consisting of Si_(1-x)Ge_x, Si_(1-x)C_x or Si_(1-x-y)B_xGe_y, where x is between 0.1 and 0.8, and y is between 0.1 and 0.8,

the source and drain regions are adjacent to said gate structure;

source and drain region are at least partially in said stressor regions.