Method for manufacturing semiconductor devices

• US 20070026611A1
• Filed: 08/24/2005
• Published: 02/01/2007
• Est. Priority Date: 07/26/2005
• Status: Active Grant

• Current Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Original Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Inventors: Arase, Takao, Saito, Go, Shimomura, Takahiro, Nishida, Toshiaki
• Granted Patent: US 7,364,956 B2
• Time in Patent Office: Days
• US Class Current: 438/261
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Abstract

A method for manufacturing semiconductor devices includes a step of etching a sample including an interlayer insulating layer containing Al₂O₃ and a polysilicon or SiO₂ layer in contact with the interlayer insulating layer using a plasma etching system. The interlayer insulating layer is etched with a gas mixture containing BCl₃, Ar, and CH₄ or He. The gas mixture further contains Cl₂. The interlayer insulating layer is etched in such a manner that a time-modulated high-frequency bias voltage is applied to the sample. The interlayer insulating layer is etched in such a manner that the sample is maintained at a temperature of 100° C. to 200° C. The interlayer insulating layer and the polysilicon or SiO₂ layer are separately etched in different chambers.

Claims

1. A method for manufacturing semiconductor devices comprising:

a step of etching a sample including an interlayer insulating layer containing Al₂O₃ and a polysilicon or SiO₂ layer in contact with the interlayer insulating layer using a plasma etching system,

wherein the interlayer insulating layer is etched with a gas mixture containing BCl₃, Ar, and CH₄ or He.

2. The method according to claim 1, wherein the gas mixture further contains Cl₂.

3. The method according to claim 1, wherein the interlayer insulating layer is etched in such a manner that a time-modulated high-frequency bias voltage is applied to the sample.

4. The method according to claim 1, wherein the interlayer insulating layer is etched in such a manner that the sample is maintained at a temperature of 100°

C. to 200°

C.

5. The method according to claim 1, wherein the interlayer insulating layer is etched in such a manner that the sample is maintained at a temperature of 100°

C. to 200°

C. and the interlayer insulating layer and the polysilicon or SiO₂ layer are separately etched in different chambers.