Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process

• US 20070032084A1
• Filed: 09/14/2006
• Published: 02/08/2007
• Est. Priority Date: 08/08/2005
• Status: Active Grant

• Current Assignee: Silicon Genesis
• Original Assignee: Silicon Genesis
• Inventors: Henley, Francois
• Granted Patent: US 7,351,644 B2
• Time in Patent Office: Days
• US Class Current: 438/692
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2924/19041 being a capacitor

Abstract

A method for fabricating one or more devices, e.g., integrated circuits. The method includes providing a substrate (e.g., silicon), which has a thickness of semiconductor material and a surface region. The substrate also has a cleave plane provided within the substrate to define the thickness of semiconductor material. The method includes joining the surface region of the substrate to a first handle substrate. In a preferred embodiment, the first handle substrate is termed a “thin” substrate, which provides suitable bonding characteristics, can withstand high temperature processing often desired during the manufacture of semiconductor devices, and has desirable de-bonding characteristics between it and a second handle substrate, which will be described in more detail below. In a preferred embodiment, the first handle substrate is also thick enough and rigid enough to allow for cleaving according to a specific embodiment.

Claims

1-35. -35. (canceled)

36. A method comprising:

initiating controlled cleaving at a portion of a cleave plane to detach a thickness of a semiconductor material from a substrate while the thickness remains joined to a frontside of a first handle substrate, thereby exposing a surface of the thickness of semiconductor material;

joining a backside of the first handle substrate to a second handle substrate;

forming an integrated circuit device on the surface;

forming a planarized layer overlying the surface and the integrated circuit device;

joining the planarized layer to a third handle substrate; and

removing the second handle substrate from the first handle substrate including the thickness of semiconductor material, while the third handle substrate remains joined to the planarized layer.

37. The method of claim 36 wherein the integrated circuit device is selected from a MOSFET, a CMOS device, an active device, a capacitor, a resistor, and an inductor.

38. The method of claim 36 wherein the cleave plane comprises a plurality of particles, a strained region, a weakened region, or a deposited material.

39. The method of claim 38 wherein the a plurality of particles are hydrogen bearing particles.

40. The method of claim 38 wherein the cleave plane is formed by implantation of hydrogen into the substrate.

41. The method of claim 38 wherein the cleave plane is formed by implantation of helium into the substrate.

42. The method of claim 36 further comprising patterning the first handle substrate coupled to the third handle substrate to form one or more via structures.

43. The method of claim 36 wherein the joining comprises a bonding process selected from a glue process, an electro static process, a non-organic glue process, an anodic process, a plasma activation process, or a wet activation process.

44. The method of claim 36 wherein the substrate is selected from a silicon wafer, a silicon on insulator wafer, a silicon bearing material, a single layer substrate, and a multi-layer substrate..

45. The method of claim 36 wherein the planarized layer is selected from an oxide containing material, a nitride containing material, spin-on-glass, and metal.

46. The method of claim 36 further comprising subjecting the planarized layer and the third handle substrate to a cleaning solution.

47. The method of claim 36 wherein the second handle substrate is removed from the first handle substrate by an etching process, a cleaving process, a grinding process, or a chemical mechanical polishing process.

48. A method for fabricating a device on a substrate, the method comprising:

joining a surface region of a substrate to a first handle substrate;

initiating a controlled cleaving action at a portion of a cleave plane in the substrate to detach the thickness of semiconductor material from the substrate while the thickness remains joined to the first handle substrate;

joining a backside of the first handle substrate to a second handle substrate;

forming a device on a portion of the thickness of semiconductor material;

forming a planarized surface region overlying the thickness;

joining the planarized surface region to a face of a third handle substrate; and

removing the second handle substrate from the first handle substrate including the thickness of semiconductor material, while the face of the third handle substrate remains joined to the planarized surface region.

49. The method of claim 48 wherein the first handle substrate is a silicon substrate having a thickness of 300 microns and less.

50. The method of claim 48 wherein the second handle substrate firmly engages with the first handle substrate to withstand a temperature of about 400 degrees Celsius and greater.

51. The method of claim 48 wherein the joining of the between the first handle substrate and the second handle substrate has a bond strength ranging from about 200-500 milliJoules per square meter.

52. The method of claim 48 further comprising patterning the first handle substrate coupled to the third handle substrate to form one or more via structures, the one or more via structures having a width to depth ratio ranging from about 1/20 to about 1/30.

53. The method of claim 48 wherein the first substrate, second substrate, and thickness of material are characterized by a total thickness ranging at about 825 microns and a diameter of about 200 millimeters.

54. The method of claim 48 wherein the controlled cleaving action forms a single propagating cleave front on the portion of the cleave plane.

55. The method of claim 48 wherein the controlled cleaving action forms more than one propagating cleave fronts on the portion of the cleave plane.

56. The method of claim 48 wherein the first handle substrate has a thickness ranging from about 5 microns to about 10 microns.

57. The method of claim 48 wherein the second handle substrate is selected from a silicon substrate, a polysilicon substrate and a quartz substrate.

58. The method of claim 48 wherein the device comprises a MOSFET, a CMOS device, an active device, a capacitor, a resistor, an inductor, a photonic device, a piezoelectric device, a microelectromechanical system, a sensor, an actuator, a solar cell, a biological device, or a display device.

59. The method of claim 48 wherein the removing comprises using a mechanical separation process to remove the second handle substrate from the first handle substrate.

60. The method of claim 48 wherein the first handle substrate is selected from a silicon substrate, a polysilicon substrate and a quartz substrate.