METHOD AND SYSTEM FOR FAST CONTEXT BASED ADAPTIVE BINARY ARITHMETIC CODING

• US 20070040711A1
• Filed: 08/22/2005
• Published: 02/22/2007
• Est. Priority Date: 08/22/2005
• Status: Active Grant

• Current Assignee: Streaming Networks PVT Limited
• Original Assignee: Streaming Networks PVT Limited
• Inventors: Ziauddin, Syed Muhammad
• Granted Patent: US 7,221,296 B2
• Time in Patent Office: Days
• US Class Current: 341/51
• CPC Class Codes: H03M 7/4006 Conversion to or from arithmetic code

Abstract

A method for efficient and fast implementation of context-based adaptive binary arithmetic encoding in H.264/AVC video encoders is disclosed. The H.264/AVC video standard supports two entropy coding mechanisms. These include Context Adaptive Binary Arithmetic Coding (CABAC) and Context Adaptive Variable Length Coding (CAVLC). The entropy coding efficiency of CABAC exceeds that of CAVLC by a clear margin. The method further provides techniques that make the implementation of CABAC on digital signal processors (DSPs) and other processing devices significantly faster. In one aspect, the method increases decoupling between the binarization process and the arithmetic encoding process from bit level to single or multiple syntax element(s) level. The binarized data is provided to the arithmetic encoding engine in bulk, thereby significantly reducing the overhead due to procedure calls. In another aspect, a CABAC arithmetic encoding engine format is provided which decreases data writing overhead and better exploits parallelism in the encoding process. This aspect is particularly advantageous to, for example, very long instruction word (VLIW) DSPs and media processors. In yet another aspect, the method discloses efficient CABAC binarization schemes for syntax elements.

Claims

1. A method for providing context-based adaptive binary arithmetic CABAC coding, the method comprising:

performing binarization on one or more syntax elements to obtain a binary sequence;

providing data bits of the said binary sequence to an arithmetic encoding unit in bulk;

performing binarization on one or more syntax elements to generate exp Golomb code by converting mapped syntax-element values to corresponding floating point type values;

performing re-normalization of CABAC encoding by restructuring the re-normalization into two processing units including an arithmetic encoding unit and a bit writing unit; and

configuring the bit writing unit to format signal bits into a multiple-bit sequence, and write multiple bits simultaneously during an execution of a bit writing loop.

2. The method of claim 1 wherein:

a single syntax element or a plurality of syntax elements are binarized to obtain a binary sequence;

context data is generated for the bits of the said binary sequence; and

the bits of the said binary sequence and the corresponding context data are provided to the arithmetic encoding unit in bulk or in chunks of suitable sizes.

4. The method of claim 1 wherein the binarization on order-0 and order-3 exp Golomb code suffixes is carried out by converting mapped syntax-element values to corresponding floating point type numbers in single or double precision arithmetic and using an exponent of the floating point type numbers to determine the length and code value of the binary sequence.

6. The method of claim 1 wherein the bit writing unit is separated from the arithmetic encoding unit to increase parallelism and reduce branching in CABAC regular mode renormalization process.

7. The method of claim 6 wherein the bit writing unit of the re-normalization process in CABAC regular encoding mode is configured to format the first bit and the following bits into a multiple bit sequence and write multiple bits simultaneously during one execution of a bit writing loop.

8. The method of claim 6 wherein the bit writing unit of the re-normalization process in CABAC regular encoding mode is configured to format the first bit and the following bits into a multiple bit sequence, divide the bit sequence into chunks of suitable sizes, and write multiple bits simultaneously during each iteration of a bit writing loop.

9. The method of claim 6 wherein the bit writing unit of the re-normalization process in CABAC regular encoding mode is configured to write multiple bits simultaneously during each iteration of a bit writing loop without requiring any intermediate storage.

10. The method of claim 1 wherein a multiple-bit CABAC bypass or regular mode encoding routine performs arithmetic encoding on all the bits of a binary sequence and generates output for the entire binary sequence.

11. The method of claim 1 wherein the bit writing unit is separated from the arithmetic unit to increase parallelism and reduce branching in CABAC bypass encoding mode.

12. The method of claim 11 wherein the bit writing unit of the re-normalization process in CABAC bypass encoding mode is configured to format the first bit and the following bits into a multiple bit sequence and write multiple bits simultaneously during one execution of a bit writing loop.

13. The method of claim 11 where the bit writing unit of the re-normalization process in CABAC bypass encoding mode is configured to format the first bit and the following bits into a multiple bit sequence, divide the bit sequence into chunks of suitable sizes, and write multiple bits simultaneously during each iteration of a bit writing loop.

14. The method of claim 11 wherein the bit writing unit of the re-normalization process in CABAC bypass encoding mode is configured to write multiple bits simultaneously during each iteration of a bit writing loop without requiring any intermediate storage.

15. A digital signal processor configured to execute the method as recited in claim 1.

16. The method of claim 15 wherein the digital signal processor is a very long instruction word (VLIW) processor.

17. A video encoder configured to execute the method as recited in claim 1.

18. The method of claim 1, wherein the binarization of data elements to order-k exp Golomb code suffices is carried out by converting mapped data-element values to corresponding floating point type numbers in single or double precision arithmetic and using an exponent of the floating point type numbers to determine the length and code value of the binary sequence.

3. (canceled)

5. (canceled)