METHODS AND SYSTEMS FOR GENERATING LATCH CLOCK USED IN MEMORY READING
First Claim
1. A method for generating, from an internal clock, a latch clock used in reading a memory, the method comprising:
- storing data with a first logic level into a first address of the memory and data with a second logic level into a second address of the memory;
generating a read data signal by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory;
varying a delay parameter until at least an edge of the internal clock signal and any edge of the read data signal are aligned; and
generating the latch clock according to the delay parameter and the internal clock.
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Accused Products
Abstract
Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. Varying a delay parameter until at least an edge of the internal clock signal and any edge of the read data signal are aligned. Finally, the latch clock is generated according to the delay parameter and the internal clock.
11 Citations
12 Claims
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1. A method for generating, from an internal clock, a latch clock used in reading a memory, the method comprising:
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storing data with a first logic level into a first address of the memory and data with a second logic level into a second address of the memory;
generating a read data signal by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory;
varying a delay parameter until at least an edge of the internal clock signal and any edge of the read data signal are aligned; and
generating the latch clock according to the delay parameter and the internal clock. - View Dependent Claims (2, 3, 4, 5)
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6. A memory subsystem, comprising:
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a memory; and
a memory controller comprising an internal clock, the memory controller operative in a calibration mode to store data with a first logic level into a first address of the memory, to store data with a second logic level into a second address of the memory, to generate a read data signal by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory, to adjust a delay parameter until any edge of the read data signal and at least one edge of the internal clock signal are aligned, and to generate a latch clock according to the delay parameter and the internal clock. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A memory subsystem, comprising:
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a memory; and
a memory controller providing a latch clock and accessing the memory with reference to the latch clock, comprising;
means for storing data with a first logic level into a first address of the memory, and storing data with a second logic level into a second address of the memory;
means for generating a read data signal by issuing continuous read commands to repeatedly retrieve the data at the first and the second addresses of the memory;
means for varying a delay parameter until any edge of the read data signal and at least one edge of the internal clock signal are aligned; and
means for generating the latch clock according to the delay parameter and the internal clock.
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Specification