Digital transmitter

• US 20070041469A1
• Filed: 08/31/2006
• Published: 02/22/2007
• Est. Priority Date: 06/20/1997
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: University of North Carolina At Chapel Hill (University of North Carolina System)
• Inventors: Dally, William
• Granted Patent: US 7,580,474 B2
• Time in Patent Office: Days
• US Class Current: 375/296
• CPC Class Codes: H04B 1/0483 Transmitters with multiple parallel paths
• CPC Class Codes: H04B 1/1081 Reduction of multipath noise by equalising H04B7/005
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 3/04 Control of transmission; Equalising
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03025 using a two-tap delay line
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 27/01 Equalisers baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005

Abstract

An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

Claims

1. A circuit comprising:

a semiconductor chip;

a transmitter circuit disposed on the chip, the transmitter circuit being operable to accept a digital input signal including a plurality of bits and send an output signal including a series of output bit signals, each bit of the digital input signal being represented by a single output bit signal, the transmitter being operable to provide the output signal with an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz, each output bit signal having;

(i) a first signal level when the bit represented by that output bit signal has a particular digital value and that particular digital value is the same as the digital value of a bit represented by an immediately preceding output bit signal; and

(ii) a second signal level when the bit represented by that output bit signal has the particular digital value and that particular digital value is different from the digital value of a bit represented by an immediately preceding output bit signal.

2. The circuit as claimed in claim 1 wherein the first signal level has a magnitude less than a magnitude of the second signal level.

3. The circuit as claimed in claim 1 further comprising a memory, the transmitter circuit being coupled to the memory to accept the digital input signal from the memory.

4. The circuit as claimed in claim 1 further comprising a processor, the transmitter circuit being coupled to the processor to accept the digital input signal from the processor.

5. The circuit as claimed in claim 1 further comprising a peripheral, the transmitter circuit being coupled to the peripheral to accept the digital input signal from the peripheral.

6. The circuit as claimed in claim 1 further comprising a hub, the transmitter circuit being coupled to the hub to accept the digital input signal from the hub.

7. The circuit as claimed in claim 1 wherein the first and second signal levels are fixed.

8. The circuit as claimed in claim 1 wherein the first and second signal levels are reprogrammable.

9. The circuit as claimed in claim 1 wherein the first and second signal levels are adaptive.

10. An apparatus comprising a plurality of elements selected from the group consisting of processors, memories, hubs and peripherals, at least one signal path for conveying information between the elements, and at least one circuit as claimed in claim 1, the transmitter circuit being coupled to one of the elements for acceptance of the digital input signal from that one of the elements and being coupled to the signal path for transmission of the output bit signals along the signal path to another one of the elements.

11. The apparatus as claimed in claim 10 further comprising a cabinet, the elements, the at least one transmitter circuit and the at least one signal path being disposed within the cabinet.

12. The apparatus as claimed in claim 10 wherein the signal path has a length of up to 10 meters.

13. The apparatus as claimed in claim 10 wherein the signal path is a signal path on a circuit board.

14. A circuit comprising:

a semiconductor chip;

a transmitter circuit disposed on the chip, the transmitter circuit being operable to accept a digital input signal including a plurality of bits and send an output signal including a series of output bit signals, each bit of the digital input signal being represented by a single output bit signal, the transmitter being operable to provide the output signal with an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz, each output bit signal having a signal level which is a function of the value of the bit represented by that output bit signal and the values of one or more bits represented by one or more preceding output bit signals.

15. The circuit as claimed in claim 14 wherein the function emphasizes high frequency components of the output signal relative to low frequency components of the output signal.

16. The circuit as claimed in claim 14 wherein the function is such that an output bit signal representing a bit having a value different from the values of bits represented by the one or more preceding output bit signals will have a signal level of greater magnitude than an output bit signal representing a bit having the same value as the values of the bits represented by the one or more preceding output bit signals.

17. The circuit as claimed in claim 14 further comprising a memory, the transmitter circuit being coupled to the memory to accept the digital input signal from the memory.

18. The circuit as claimed in claim 14 further comprising a processor, the transmitter circuit being coupled to the processor to accept the digital input signal from the processor.

19. The circuit as claimed in claim 14 further comprising a peripheral, the transmitter circuit being coupled to the peripheral to accept the digital input signal from the peripheral.

20. The circuit as claimed in claim 14 further comprising a hub, the transmitter circuit being coupled to the hub to accept the digital input signal from the hub.

21. The circuit as claimed in claim 14 wherein the function is fixed.

22. The circuit as claimed in claim 14 wherein the function is reprogrammable.

23. The circuit as claimed in claim 14 wherein the function is adaptive.

24. An apparatus comprising a plurality of elements selected from the group consisting of processors, memories, and peripheral, at least one signal path for conveying information between the elements, and at least one circuit as claimed in claim 14, the transmitter circuit being coupled to one of the elements for acceptance of the digital input signal from that one of the elements and being coupled to the signal path for transmission of the output bit signals along the signal path to another one of the elements.

25. The apparatus as claimed in claim 24 further comprising a cabinet, the elements, the at least one transmitter circuit and the at least one signal path being disposed within the cabinet.

26. The apparatus as claimed in claim 24 wherein the signal path has a length of up to 10 meters.

27. The apparatus as claimed in claim 24 wherein the signal path is a signal path on a circuit board.

28. A component comprising:

a semiconductor chip;

a transmitter circuit within the chip, the transmitter circuit being operable to transmit an output signal including a series of signal levels, each signal level having a discrete signal level value, each signal level denoting a digital value, the number of different signal level values in the output signal being greater than the number of different digital values denoted by the output signal, the signal level values being selected so that;

(i) a signal level denoting a particular digital value has one signal level value when the particular digital value is the same as the digital value denoted by a preceding signal level; and

(ii) a signal level denoting the particular digital value has another signal level value when the particular digital value is different from the digital value denoted by a preceding signal level.

29. The component as claimed in claim 28 wherein the chip has I/O connections and the transmitter circuit is coupled to one or more of the I/O connections to send the output signal through the one or more I/O connections.

30. The component as claimed in claim 29 wherein the transmitter circuit is operable to send the signal level values as currents.

31. The component as claimed in claim 30 wherein the transmitter circuit is operable to send the signal level values as opposite currents through a pair of I/O connections.

32. The component as claimed in claim 28 wherein the transmitter circuit is operable to send the output signal with an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz.

33. The component as claimed in claim 28 wherein the transmitter circuit is operable to send the output signal such that each signal level represents more than one bit of information.

34. The component as claimed in claim 28 further comprising an element selected from the group consisting of processors, memories, hubs, and peripherals, the transmitter circuit being coupled to the element to accept a digital signal from the element and to form the output signal so that the output signal represents the digital signal.

35. An apparatus comprising a signal path, an additional chip and a component as claimed in claim 34, the transmitter circuit being operable to send the output signal in nonmodulated form along the signal path to the additional chip.

36. A method of transmitting digital information the steps comprising:

providing a digital signal including a plurality of digital values within a semiconductor chip; and

transmitting an output signal from the chip representing the digital signal, the output signal including a series of signal levels, each signal level having a discrete signal level value, each signal level denoting a digital value, the number of different signal level values in the output signal being greater than the number of different digital values denoted by the output signal, the signal level values being selected so that;

(i) a signal level denoting a particular digital value has one signal level value when the particular digital value is the same as the digital value denoted by a preceding signal level; and

(ii) a signal level denoting the particular digital value has another signal level value when the particular digital value is different from the digital value denoted by a preceding signal level.

37. The method as claimed in claim 36 wherein the transmitting step includes sending the signal level values as currents.

38. The method as claimed in claim 37 wherein the transmitting step includes sending the signal level values as opposite currents along a transmission line including a pair of conductors.

39. The method as claimed in claim 36 wherein the output signal has an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz.

40. The method as claimed in claim 36 in which the step of providing the digital signal includes operating an element within the chip, the element being selected from the group consisting of processors, memories, hubs, and peripherals.

41. The method as claimed in claim 36 wherein the each signal level in the output signal represents more than one bit of information in the digital signal.