Circuit, System, and Method for Multiplexing Signals with Reduced Jitter

• US 20070053475A1
• Filed: 08/29/2006
• Published: 03/08/2007
• Est. Priority Date: 09/02/2005
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Li, Gabriel
• Granted Patent: US 7,609,799 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03K 17/002 Switching arrangements with several input- or output terminals code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits

Abstract

A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply noise injection may be eliminated by: (i) separating the multiplexing function into three separate logic gates and (ii) allowing only one switching input per logic gate. In some cases, jitter may be further reduced by distributing the logic gates across three distinct power domains. In other words, the logic gate inputs may be further isolated by gating each signal in its own power domain. In addition, the multiplexer circuit provides built in delay matching by utilizing three substantially identical logic gates.

Claims

1. A circuit comprising:

a first logic gate arranged within a first power supply domain and coupled for receiving a first signal;

a second logic gate arranged within a second power supply domain and coupled for receiving a second signal;

a logic block arranged within a third power supply domain and coupled for supplying a control signal to the first and second logic gates for deactivating one of the first and second signals; and

a third logic gate arranged within a fourth power supply domain and coupled to outputs of the first and second logic gates for transmitting either the first signal or the second signal, whichever has not been deactivated by the logic block.

2. The circuit of claim 1, wherein the first, second and third logic gates each comprise a two-input NAND gate.

3. The circuit of claim 1, wherein the first, second and third logic gates each comprise a two-input NOR gate.

4. The circuit of claim 1, wherein the control signal is coupled to a first input of the first logic gate and a first input of the second logic gate.

5. The circuit of claim 4, wherein the first signal is coupled to a second input of the first logic gate, and the second signal is coupled to a second input of the second logic gate.

6. The circuit of claim 5, wherein the first and second signals comprise clock signals.

7. The circuit of claim 5, wherein the first and second signals comprise data signals.

8. The circuit of claim 5, wherein outputs of the first and second logic gates are respectively coupled to a first and second input of the third logic gate in the third power supply domain.

9. The circuit of claim 8, wherein an output of the third logic gate is coupled to a buffer circuit arranged within a fourth power supply domain of the circuit.

10. A system, comprising:

a circuit comprising three logic gates and a logic block, each arranged within a separate power domain, wherein;

a first of the three logic gates is coupled for receiving a first signal;

a second of the three logic gates is coupled for receiving a second signal; and

a third of the three logic gates is coupled for receiving only one of the first and second signals, depending on a state of a control signal supplied to the first and second logic gates from the logic block; and

at least one system component coupled to an output of the third logic gate for receiving the only one of the first and second signals.

11. The system of claim 10, wherein the first, second and third logic gates each comprise a NAND gate.

12. The system of claim 10, wherein the first, second and third logic gates each comprise a NOR gate.

13. The system of claim 10, wherein the first, second and third logic gates each comprise an identical logic gate.

14. The system of claim 10, wherein the first and second signals comprise clock signals.

15. The system of claim 14, further comprising one or more phase shift apparatuses coupled to the circuit for supplying the first and second signals thereto.

16. The system of claim 15, wherein the one or more phase shift apparatuses each comprise a device selected from a group comprising a phase locked loop (PLL) device and a delay locked loop (DLL) device.

17. A method for multiplexing signals with reduced jitter, the method comprising:

supplying a first signal to a first logic gate and a second signal to a second logic gate;

deactivating one of the first or second signals by supplying a control signal to the first and second logic gates; and

forwarding an active one of the first or second signals to a third logic gate, wherein the steps of deactivating and forwarding enable the first and second signals to be multiplexed with reduced jitter.

18. The method of claim 17, wherein the first, second and third logic gates are spaced apart from one another and respectively arranged within a first, second and third power domain.

19. The method of claim 17, wherein the first and second signals comprise clock signals.

20. The method of claim 17, wherein the first and second signals comprise data signals.