Semiconductor Device

• US 20070064511A1
• Filed: 10/30/2006
• Published: 03/22/2007
• Est. Priority Date: 12/12/2003
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Atsumi, Tomoaki, Shionoiri, Yutaka, Kato, Kiyoshi
• Granted Patent: US 7,430,146 B2
• Time in Patent Office: Days
• US Class Current: 365/203
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

It is an object of the present invention to provide a semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. A semiconductor device of the invention has three factors of a data holding unit, a precharge unit and a delay unit. The data holding unit comprises a plurality of memory cells. The precharge unit comprises a precharge potential line, a precharge signal line and a plurality of switches. The delay unit comprises a plurality of transistors. In addition, it has one or both of an address selecting unit having a column-decoder and a row-decoder and a display unit having a plurality of pixels, as well as the three factors.

Claims

1. A semiconductor device comprising:

an antenna formed on a first substrate;

an IC chip formed on a second substrate and mounted on the first substrate, the IC chip comprising;

a memory unit having a first thin film transistor, the memory unit comprising;

a data holding unit having a plurality of memory cells; and

an address selecting unit comprising;

a column-decoder; and

a low-decoder;

a control unit having a second thin film transistor formed on the second substrate, the control unit configured to control the memory unit; and

a power generation unit having a third thin film transistor formed on the second substrate, the power generation unit configured to supply a power to the memory unit and the control unit.

2. The semiconductor device according to claim 1,

wherein the IC chip is sandwiched between the first substrate and the second substrate.

3. The semiconductor device according to claim 1,

wherein the first substrate and the second substrate comprise a resin material.

4. The semiconductor device according to claim 1,

wherein the control unit comprises a CPU.

5. The semiconductor device according to claim 1,

wherein the data holding unit comprises a read only memory.

6. The semiconductor device according to claim 1,

wherein the data holding unit comprises a random access memory.

7. A semiconductor device comprising:

an antenna formed on a substrate;

an IC chip formed on a substrate, the IC chip comprising;

a memory unit having a first thin film transistor, the memory unit comprising;

a data holding unit having a plurality of memory cells; and

an address selecting unit comprising;

a column-decoder; and

a low-decoder;

a control unit having a second thin film transistor formed on the second substrate, the control unit configured to control the memory unit; and

a power generation unit having a third thin film transistor formed on the substrate, the power generation unit configured to supply a power to the memory unit and the control unit.

8. The semiconductor device according to claim 7,

wherein the substrate comprises a resin material.

9. The semiconductor device according to claim 7,

wherein the control unit comprises a CPU.

10. The semiconductor device according to claim 7,

wherein the data holding unit comprises a read only memory.

11. The semiconductor device according to claim 7,

wherein the data holding unit comprises a random access memory.

12. A semiconductor device comprising:

an antenna formed on a first substrate;

an IC chip formed on a second substrate and mounted on the first substrate, the IC chip comprising;

a memory unit having a first thin film transistor, the memory unit comprising;

a data holding unit having a plurality of memory cells;

an address selecting unit comprising;

a column-decoder; and

a low-decoder;

a precharge unit electrically connected to the data holding unit, comprising;

a precharge potential line;

a plurality of switches electrically connected to the precharge potential line; and

a precharge signal line electrically connected to the plurality of switches; and

a delay unit electrically connected to the precharge signal line;

a control unit having a second thin film transistor formed on the second substrate, the control unit configured to control the memory unit; and

a power generation unit having a third thin film transistor formed on the second substrate, the power generation unit configured to supply a power to the memory unit and the control unit.

13. The semiconductor device according to claim 12,

wherein the IC chip is sandwiched between the first substrate and the second substrate.

14. The semiconductor device according to claim 12,

wherein the first substrate and the second substrate comprise a resin material.

15. The semiconductor device according to claim 12,

wherein the control unit comprises a CPU.

16. The semiconductor device according to claim 12,

wherein the data holding unit comprises a read only memory.

17. The semiconductor device according to claim 12,

wherein the data holding unit comprises a random access memory.

18. The semiconductor device according to claim 12,

wherein the delay unit comprises a inverter.

19. A semiconductor device comprising:

an antenna formed on a substrate;

an IC chip formed on a substrate, the IC chip comprising;

a memory unit having a first thin film transistor, the memory unit comprising;

a data holding unit having a plurality of memory cells;

an address selecting unit comprising;

a column-decoder; and

a low-decoder;

a precharge unit electrically connected to the data holding unit, comprising;

a precharge potential line;

a plurality of switches electrically connected to the precharge potential line; and

a precharge signal line electrically connected to the plurality of switches; and

a delay unit electrically connected to the precharge signal line;

a control unit having a second thin film transistor formed on the second substrate, the control unit configured to control the memory unit; and

a power generation unit having a third thin film transistor formed on the substrate, the power generation unit configured to supply a power to the memory unit and the control unit.

20. The semiconductor device according to claim 19,

wherein the substrate comprises a resin material.

21. The semiconductor device according to claim 19,

wherein the control unit comprises a CPU.

22. The semiconductor device according to claim 19,

wherein the data holding unit comprises a read only memory.

23. The semiconductor device according to claim 19,

wherein the data holding unit comprises a random access memory.

24. The semiconductor device according to claim 19,

wherein the delay unit comprises a inverter.