Compact integration of LC resonators

• US 20070069835A1
• Filed: 09/29/2005
• Published: 03/29/2007
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kamgaing, Telesphor
• Granted Patent: US 7,548,138 B2
• Time in Patent Office: Days
• US Class Current: 333/185
• CPC Class Codes: H01F 2017/0046 with a conductive path having a bridge
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H03H 2001/0085 Multilayer, e.g. LTCC, HTCC, green sheets inside PCB filters H05K
• CPC Class Codes: H03H 5/02 without voltage- or current-dependent elements

Abstract

A technique to provide a compact integration of inductor-capacitor resonator a capacitor having a top plate and a bottom plate embedding a dielectric layer. The top and bottom plates are substantially parallel to each other. An inductor having a first end is coupled to the capacitor at the bottom plate. The inductor has N turns surrounding the bottom plate in a spiral geometry. The inductor is co-planar to one of the top and bottom plates and ends at a second end.

Claims

1. An apparatus comprising:

a capacitor having a top plate and a bottom plate embedding a dielectric layer, the top and bottom plates being substantially parallel to each other; and

an inductor having a first end coupled to the capacitor at the bottom plate and having N turns surrounding the bottom plate in a spiral geometry, the inductor being co-planar to one of the top and bottom plates and ending at a second end.

2. The apparatus of claim 1 further comprising:

a first feed coupled to the top plate; and

a second feed coupled to the second end such that the capacitor and the inductor are electrically in series between the first and second feeds.

3. The apparatus of claim 2 further comprising:

a via connecting between the first feed and the top to provide a connection point.

4. The apparatus of claim 1 further comprising:

a first feed coupled to the bottom plate at a bottom via; and

a second feed coupled to the top plate and the second end at a first top via such that the capacitor and the inductor are electrically in parallel between the first and the second feeds.

5. The apparatus of claim 4 further comprising:

a second top via connecting between the top plate and the second feed to provide a connection point.

6. The apparatus of claim 4 wherein the bottom plate is larger than the top plate.

7. The apparatus of claim 1 wherein N ranges from ½

to 10.

13. The method of claim 1 wherein the bottom plate is larger than the top plate.

8. A method comprising:

forming a capacitor having a top plate and a bottom plate embedding a dielectric layer, the top and bottom plates being substantially parallel to each other; and

surrounding the bottom plate by an inductor having a first end coupled to the capacitor at the bottom plate and having N turns in a spiral geometry, the inductor being co-planar to one of the top and bottom plates and ending at a second end.

9. The method of claim 8 further comprising:

connecting a first feed to the top plate; and

connecting a second feed to the second end such that the capacitor and the inductor are electrically in series between the first and second feeds.

10. The method of claim 9 further comprising:

connecting a via between the first feed and the top plate to provide a connection point.

11. The method of claim 8 further comprising:

connecting a first feed to the bottom plate at a bottom via; and

connecting a second feed to the top plate and the second end at a first top via such that the capacitor and the inductor are electrically in parallel between the first and the second feeds.

12. The method of claim 11 further comprising:

connecting a second top via between the top plate and the second feed to provide a connection point.

14. The method of claim 8 wherein N ranges from ½

to 10.

15. A system comprising:

a base-band processing unit to process base-band data;

and intermediate frequency (IF) processing unit coupled to the base-band processing unit to process IF signals; and

a system on package (SOP) coupled to the IF processing unit to process radio frequency (RF) signals;

the SOP comprising multiple layers having an antenna layer, an embedded passives (EP) layer, and a filter layer, the filter layer comprising;

a capacitor having a top plate and a bottom plate embedding a dielectric layer, the top and bottom plates being substantially parallel to each other, and

an inductor having a first end coupled to the capacitor at the bottom plate and having N turns surrounding the bottom plate in a spiral geometry, the inductor being co-planar to the bottom plate and ending at a second end.

16. The system of claim 15 wherein the filter layer further comprises:

a first feed coupled to the top plate; and

a second feed coupled to the second end such that the capacitor and the inductor are electrically in series between the first and second feeds.

17. The system of claim 16 wherein the filter layer further comprises:

a via connecting between the first feed and the top plate to provide a connection point.

18. The system of claim 15 wherein the filter layer further comprises:

a first feed coupled to the bottom plate at a bottom via; and

a second feed coupled to the top plate and the second end at a first top via such that the capacitor and the inductor are electrically in parallel between the first and the second feeds.

19. The system of claim 18 wherein the filter layer further comprises:

a second top via connecting between the top plate and the second feed to provide a connection point.

20. The system of claim 18 wherein the bottom plate is larger than the top plate.