Static random access memory device having bit line voltage control for retain till accessed mode and method of operating the same

• US 20070070773A1
• Filed: 09/28/2005
• Published: 03/29/2007
• Est. Priority Date: 09/28/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore
• Granted Patent: US 8,064,271 B2
• Time in Patent Office: Days
• US Class Current: 365/229
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A static random-access memory (SRAM) and a method of controlling bit line voltage. In one embodiment, the SRAM includes: (1) an array of SRAM cells organized in rows and columns, (2) bit lines associated with the columns, (3) a high voltage power supply configured to supply a high supply voltage, (4) a low voltage power supply configured to supply a low supply voltage, (5) bit line precharge circuitry configured to precharge at least one of the bit lines to a first voltage and (6) standby circuitry configured to maintain a voltage of the at least one bit line at at least a second voltage, the second voltage being lower than the first voltage and higher than the low supply voltage.

Claims

1. A static random-access memory (SRAM), comprising:

an array of SRAM cells organized in rows and columns;

bit lines associated with said columns;

a high voltage power supply configured to supply a high supply voltage;

a low voltage power supply configured to supply a low supply voltage;

bit line precharge circuitry configured to precharge at least one of said bit lines to a first voltage; and

standby circuitry configured to maintain a voltage of said at least one bit line at at least a second voltage, said second voltage being lower than said first voltage and higher than said low supply voltage.

2. The SRAM as recited in claim 1 wherein said SRAM cells are further organized in blocks and all bit lines in an accessed one of said blocks are precharged.

3. The SRAM as recited in claim 1 wherein said bit line precharge circuitry is configured to precharge said at least one of said bit lines during an access cycle.

4. The SRAM as recited in claim 1 wherein said bit line precharge circuitry is configured to precharge said at least one of said bit lines before an access cycle.

5. The SRAM as recited in claim 1 wherein said second voltage is above about V_WL-V_tn.

6. The SRAM as recited in claim 1 wherein said first voltage is above a minimum voltage for maintaining a state of accessed SRAM cells.

7. The SRAM as recited in claim 1 wherein said second voltage is above a minimum voltage for maintaining a state of accessed SRAM cells and, in a read cycle, said bit line precharge circuitry is configured to precharge only ones of said bit lines corresponding to accessed SRAM cells to said first voltage.

8. The SRAM as recited in claim 1 wherein said second voltage is above a minimum voltage for maintaining a state of accessed SRAM cells and, in a write cycle, said bit line precharge circuitry is configured not to precharge said bit lines corresponding to accessed SRAM cells to a higher voltage.

9. The SRAM as recited in claim 1 wherein said second voltage is above a minimum voltage for maintaining a state of accessed SRAM cells and, in a read cycle, said bit line precharge circuitry is configured to precharge only said bit lines corresponding to accessed SRAM cells to a higher voltage.

10. The SRAM as recited in claim 1 wherein voltages of said bit lines are allowed to float to said second voltage when the SRAM array is not accessed.

11. The SRAM as recited in claim 1 wherein said second voltage is below a minimum voltage for maintaining a state of accessed SRAM cells and said first voltage is above said minimum voltage for maintaining said state of accessed SRAM cells.

12. The SRAM as recited in claim 1 wherein, during a write cycle, bit lines associated with non-addressed columns are precharged to a voltage above a minimum voltage for maintaining a state of accessed SRAM cells.

13. For use with a static random-access memory (SRAM) having an array of SRAM cells organized in rows and columns and bit lines associated with said columns, a method of controlling bit line voltage, comprising:

supplying a high supply voltage to said SRAM cells;

supplying a low supply voltage to said SRAM cells;

precharging at least one of said bit lines to a first voltage; and

maintaining a voltage of said at least one bit line at at least a second voltage, said second voltage being lower than said first voltage and higher than said low supply voltage.

14. The method as recited in claim 13 wherein said SRAM cells are further organized in blocks and said precharging comprises precharging all bit lines in an accessed one of said blocks.

15. The method as recited in claim 13 wherein said precharging comprises precharging said at least one of said bit lines during an access cycle.

16. The method as recited in claim 13 wherein said precharging comprises precharging said at least one of said bit lines before an access cycle.

17. The method as recited in claim 13 wherein said second voltage is above about V_WL-V_tn.

18. The method as recited in claim 13 wherein said first voltage is above a minimum voltage for maintaining a state of accessed SRAM cells.

19. The method as recited in claim 13 wherein said second voltage is above a minimum voltage for maintaining a state of accessed SRAM cells and, in a read cycle, said precharging comprises precharging only ones of said bit lines corresponding to accessed SRAM cells to said first voltage.

20. The method as recited in claim 13 wherein said second voltage is above a minimum voltage for maintaining a state of accessed SRAM cells and, in a write cycle, said precharging comprises precharging said bit lines corresponding to accessed SRAM cells to a higher voltage.