Techniques to determine integrity of information

• US 20070074092A1
• Filed: 09/23/2005
• Published: 03/29/2007
• Est. Priority Date: 09/23/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Berry, Frank, King, Steven, Dammann, Ronald
• Granted Patent: US 7,523,378 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0061 Error detection codes

Abstract

Techniques are described herein that may utilize capabilities of a data mover in order to determine an integrity validation value or perform an integrity checking operation. The integrity validation value determination and integrity checking operations may be controlled by descriptors or instructions. In some implementations, integrity validation value determination and the integrity checking operations may include determination of a cyclical redundancy checking (CRC) value.

Claims

1. A method comprising:

receiving an instruction to generate an integrity validation value over a portion of contents of a source buffer;

utilizing a retrieve capability of a data mover to retrieve at least a portion of contents identified in the instruction; and

determining an integrity validation value over a portion of the source buffer based on the instruction.

2. The method of claim 1, wherein the instruction further comprises an instruction to store at least a portion of the integrity validation value.

3. The method of claim 2, further comprising:

storing at least a portion of the integrity validation value using in part the data mover.

4. The method of claim 3, further comprising:

providing the stored portion of the integrity validation value for transmission with a network protocol unit.

5. The method of claim 1, wherein the instruction further comprises an instruction to compare at least a portion of the determined integrity validation value with a comparison value and further comprising:

retrieving the comparison value using in part the data mover; and

comparing at least a portion of the determined integrity validation value with the comparison value.

6. The method of claim 5, further comprising:

selectively making the content available in response to the at least a portion of the determined integrity validation value matching the comparison value; and

selectively performing error recovery in response to the at least a portion of the determined integrity validation value not matching the comparison value.

7. The method of claim 1, wherein the instruction further specifies an initial integrity validation value capable of use in the determining.

8. The method of claim 1, wherein the data mover comprises a direct memory access (DMA) engine.

9. The method of claim 1., wherein the determining an integrity validation value comprises determining a cyclical redundancy checking value.

10. The method of claim 1, wherein the content comprises a network protocol unit received from a network.

11. An apparatus comprising:

logic to receive an instruction to generate an integrity validation value over a portion of contents of a source buffer;

logic to utilize a retrieve capability of a data mover to retrieve at least a portion of contents identified in the instruction; and

logic to determine an integrity validation value over a portion of the source buffer based on the instruction.

12. The apparatus of claim 11, wherein the instruction further comprises an instruction to store at least a portion of the integrity validation value.

13. The apparatus of claim 12, further comprising:

logic to store at least a portion of the integrity validation value using in part the data mover.

14. The apparatus of claim 13, further comprising:

logic to provide the stored portion of the integrity validation value for transmission with a network protocol unit.

15. The apparatus of claim 11, wherein the instruction further comprises an instruction to compare at least a portion of the determined integrity validation value with a comparison value and further comprising:

logic to retrieve the comparison value using in part the data mover; and

logic to compare at least a portion of the determined integrity validation value with the comparison value.

16. The apparatus of claim 15, further comprising:

logic to selectively make the content available in response to the at least a portion of the determined integrity validation value matching the comparison value; and

logic to selectively perform error recovery in response to the at least a portion of the determined integrity validation value not matching the comparison value.

17. The apparatus of claim 11, wherein the instruction further specifies an initial integrity validation value capable of use by the logic to determine.

18. The apparatus of claim 11, wherein the data mover comprises a direct memory access (DMA) engine.

19. The apparatus of claim 11, wherein the logic to determine an integrity validation value comprises logic to determine a cyclical redundancy checking value.

20. A system comprising:

a host system comprising a processor, memory, and data mover logic, wherein the host system comprises;

logic to receive an instruction to generate an integrity validation value over a portion of contents of a source buffer,

logic to utilize a retrieve capability of the data mover to retrieve at least a portion of contents identified in the instruction, and

logic to determine an integrity validation value over a portion of the source buffer based on the instruction;

a network interface capable to transmit and receive network protocol units from a network; and

a display device.

21. The system of claim 20, wherein the instruction further comprises an instruction to store at least a portion of the integrity validation value.

22. The system of claim 20, wherein the instruction further comprises an instruction to compare at least a portion of the determined integrity validation value with a comparison value.

23. The system of claim 20, wherein the data mover comprises a direct memory access (DMA) engine.

24. The system of claim 20, wherein the logic to determine an integrity validation value comprises logic to determine a cyclical redundancy checking value.