Semiconductor devices and methods of manufacture thereof

• US 20070075351A1
• Filed: 09/30/2005
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schulz, Thomas, Luan, Hongfa
• Granted Patent: US 8,188,551 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Claims

1. A semiconductor device, comprising:

a first transistor, the first transistor including at least two first gate electrodes, the at least two first gate electrodes having a first parameter; and

a second transistor proximate the first transistor, the second transistor including at least two second gate electrodes, the at least two second gate electrodes having a second parameter, the second parameter being different than the first parameter.

2. The semiconductor device according to claim 1, wherein the first parameter comprises a first thickness, and wherein the second parameter comprises a second thickness.

3. The semiconductor device according to claim 1, wherein the first parameter comprises a first dopant level, and wherein the second parameter comprises a second dopant level.

4. The semiconductor device according to claim 1, wherein the first parameter establishes a first work function of the first transistor, wherein the second parameter establishes a second work function of the second transistor, and wherein the second work function is different than the first work function.

5. The semiconductor device according to claim 4, wherein the first transistor comprises a PMOS transistor, wherein the second transistor comprises an NMOS transistor, wherein the first work function comprises about 4.5 to 4.9 eV, and wherein the second work function comprises about 4.2 to 4.6 eV.

6. The semiconductor device according to claim 1, wherein the first transistor comprises at least one first fin structure, wherein the at least two first gate electrodes are disposed on a first sidewall of the at least one first fin structure and a second sidewall of the at least one first fin structure opposing the first sidewall of the at least one first fin structure, wherein the at least one first fin structure comprises a channel of the first transistor, wherein the second transistor comprises at least one second fin structure, wherein the at least two second gate electrodes are disposed on a first sidewall of the at least one second fin structure and a second sidewall of the at least one second fin structure opposing the first sidewall of the at least one second fin structure, wherein the at least one second fin structure comprises a channel of the second transistor.

7. The semiconductor device according to claim 6, wherein the first transistor includes three first gate electrodes, one of the three first gate electrodes being disposed on a top surface of the at least one first fin structure, and wherein the second transistor includes three second gate electrodes, one of the three second gate electrodes being disposed on a top surface of the at least one second fin structure.

8. The semiconductor device according to claim 6, further comprising:

a gate dielectric disposed between at least the sidewalls of the at least one first fin structure and the at least two first gate electrodes, and disposed between at least the sidewalls of the at least one second fin structure and the at least two second gate electrodes, wherein the gate dielectric comprises a hafnium-based dielectric, HfO₂, HfSiO, Al₂O₃, ZrO₂, ZrSiO_x, Ta₂O₅, La₂O₃, nitrides thereof, Si_xN_y, SiON, HfAlO_x, HfAlO_xN_1-x-y, ZrAlO_x, ZrAlO_xN_y, SiAlO_x, SiAlO_xN_1-x-y, HfSiAlO_x, HfSiAlO_xN_y, ZrSiAlO_x, ZrSiAlO_xN_y, combinations thereof, or combinations thereof with SiO₂.

9. The semiconductor device according to claim 1, wherein the at least two first gate electrodes and the at least two second gate electrodes comprise a first layer and a second layer disposed over the first layer, wherein the first layer comprises a metal, and wherein the second layer comprises a semiconductive material.

10. The semiconductor device according to claim 1, further comprising a plurality of the first transistors and a plurality of the second transistors, wherein each first transistor and each second transistor comprise a PMOS transistor and an NMOS transistor, respectively, of a CMOS device, wherein a first CMOS device comprises a first device type, wherein a second CMOS device comprises a second device type, wherein the second device type is different from the first device type, and wherein the first device type and the second device type comprise a high performance (HP) device, a low operation power (LOP) device, or a low standby power (LSTP) device.

11. The semiconductor device according to claim 1, wherein the first parameter comprises a first thickness and a first dopant level, wherein the second parameter comprises a second thickness and a second dopant level, wherein the second thickness is different than the first thickness, and wherein the second dopant level is different than the first dopant level.

12. A semiconductor device, comprising:

a first transistor, the first transistor including at least two first gate electrodes, the at least two first gate electrodes having a first thickness; and

a second transistor proximate the first transistor, the second transistor including at least two second gate electrodes, the at least two second gate electrodes having a second thickness, the second thickness being different than the first thickness, wherein the first thickness establishes a first work function of the at least two first gate electrodes, wherein the second thickness establishes a second work function of the at least two second gate electrodes, and wherein the second work function is different than the first work function.

13. The semiconductor device according to claim 12, wherein the at least two first gate electrodes and the at least two second gate electrodes comprise TiSiN, TaN, or TiN.

14. The semiconductor device according to claim 12, wherein the at least two first gate electrodes and the at least two second gate electrodes comprise TiSiN, TiN, TaN, Ta, Ru, HfN, W, Al, Ru, RuTa, TaSiN, NiSi_x, CoSi_x, TiSi_x, Ir, Y, Pt, Ti, PtTi, Pd, Re, Rh, borides, phosphides, or antimonides of Ti, Hf, Zr, TiAlN, Mo, MoN, ZrSiN, ZrN, HfN, HfSiN, WN, Ni, Pr, VN, TiW, partially silicided materials thereof, fully silicided materials thereof, and/or combinations thereof.

15. The semiconductor device according to claim 12, wherein the semiconductor device comprises a complementary metal oxide semiconductor (CMOS) device, wherein the first transistor comprises a PMOS transistor, wherein the second transistor comprises an NMOS transistor, and wherein the first thickness is greater than the second thickness.

16. The semiconductor device according to claim 15, wherein the first thickness is greater than the second thickness by about 50 Angstroms or more.

17. The semiconductor device according to claim 15, wherein the first thickness comprises about 500 Angstroms or less, and wherein the second thickness comprises about 100 Angstroms or less.

18. The semiconductor device according to claim 12, wherein the at least two first gate electrodes comprise the same material as the at least two second gate electrodes.

19. A semiconductor device, comprising:

a first transistor, the first transistor including at least two first gate electrodes, the at least two first gate electrodes having a first dopant level; and

a second transistor proximate the first transistor, the second transistor including at least two second gate electrodes, the at least two second gate electrodes having a second dopant level, the second dopant level being different than the first dopant level, wherein the first dopant level establishes a first work function of the at least two first gate electrodes, wherein the second dopant level establishes a second work function of the at least two second gate electrodes, and wherein the second work function is different than the first work function.

20. The semiconductor device according to claim 19, wherein the first transistor comprises a PMOS transistor, wherein the second transistor comprises an NMOS transistor, and wherein the second dopant level is greater than the first dopant level.

21. The semiconductor device according to claim 19, wherein the first transistor comprises a PMOS transistor, wherein the second transistor comprises an NMOS transistor, wherein the first dopant level comprises no implantation of a dopant species.

22. The semiconductor device according to claim 19, wherein the at least two first gate electrodes and the at least two second gate electrodes comprise TiSiN, TiN, TaN, Ta, Ru, HfN, W, Al, Ru, RuTa, TaSiN, NiSi_x, CoSi_x, TiSi_x, Ir, Y, Pt, Ti, PtTi, Pd, Re, Rh, borides, phosphides, or antimonides of Ti, Hf, Zr, TiAlN, Mo, MoN, ZrSiN, ZrN, HfN, HfSiN, WN, Ni, Pr, VN, TiW, partially silicided materials thereof, fully silicided materials thereof, and/or combinations thereof.

23. The semiconductor device according to claim 19, wherein a dopant species of at least the second dopant level comprises a material other than N.

24. The semiconductor device according to claim 19, wherein a dopant species of at least the second dopant level comprises Si, B, As, P, C, Ge, Sb, or combinations thereof.

25. The semiconductor device according to claim 19, wherein the first transistor comprises at least one first fin structure, wherein the at least two first gate electrodes are disposed on a first sidewall of the at least one first fin structure and a second sidewall of the at least one first fin structure opposing the first sidewall of the at least one first fin structure, wherein the at least one first fin structure comprises a channel of the first transistor, wherein the second transistor comprises at least one second fin structure, wherein the at least two second gate electrodes are disposed on a first sidewall of the at least one second fin structure and a second sidewall of the at least one second fin structure opposing the first sidewall, and wherein the at least one second fin structure comprises a channel of the second transistor.

26. The semiconductor device according to claim 25, wherein a dopant profile of the second transistor is different for the second gate electrode on the first sidewall of the at least one second fin structure than a dopant profile of the second gate electrode on the second sidewall of the at least one second fin structure.

27. The semiconductor device according to claim 25, wherein a dopant profile of the second transistor is substantially the same for the second gate electrode on the first sidewall of the at least one second fin structure as a dopant profile of the second gate electrode on the second sidewall of the at least one second fin structure.

28. The semiconductor device according to claim 25, wherein the first dopant level comprises a dopant species, wherein the second dopant level comprises the dopant species, wherein the first transistor includes a first source region and a first drain region formed in the at least one first fin structure, wherein the second transistor includes a second source region and a second drain region formed in the at least one second fin structure, and wherein the first source region, the first drain region, the second source region, and the second drain region comprise the dopant species.

29. A method of manufacturing a semiconductor device, the method comprising:

forming a first transistor, the first transistor including at least two first gate electrodes, the at least two first gate electrodes having a first parameter; and

forming a second transistor proximate the first transistor, the second transistor including at least two second gate electrodes, the at least two second gate electrodes having a second parameter, the second parameter being different than the first parameter.

30. The method according to claim 29, wherein the first parameter comprises a first thickness, and wherein the second parameter comprises a second thickness.

31. The method according to claim 30, further comprising, before forming the first transistor and forming the second transistor:

providing a workpiece, the workpiece comprising a silicon-on-insulator (SOI) substrate having a substrate, a buried insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the buried insulating layer, the workpiece comprising a first region and a second region;

forming at least one first fin structure and at least one second fin structure within the layer of semiconductor material within the first region and second region, respectively, each of the at least one first fin structure and each of the at least one second fin structure comprising a first sidewall and an opposing second sidewall; and

forming a gate dielectric material over at least the first and second sidewalls of the at least one first fin structure and the at least one second fin structure, wherein forming the first transistor comprises forming the at least two first gate electrodes over the gate dielectric material in the first region, wherein the at least two first gate electrodes, the gate dielectric material, and the at least one first fin structure comprise the first transistor, wherein forming the second transistor comprises forming the at least two second gate electrodes over the gate dielectric material in the second region, and wherein the at least two second gate electrodes, the gate dielectric material, and the at least one second fin structure comprise the second transistor.

32. The method according to claim 31, wherein forming the first transistor and forming the second transistor comprise depositing a first gate material over the gate dielectric material, and removing at least a portion of the first gate material from over the second transistor.

33. The method according to claim 32, wherein removing at least a portion of the first gate material from over the second transistor comprises removing all of the first gate material from over the second transistor, further comprising depositing a second gate material over at least the second transistor.

34. The method according to claim 33, wherein forming the first transistor and forming the second transistor comprise depositing a first gate material over the first transistor and the second transistor, covering the second transistor with a mask, depositing a second gate material over the first gate material and the mask, and removing the second gate material and the mask from over the second transistor.

35. The method according to claim 29, wherein the first parameter comprises a first dopant level, and wherein the second parameter comprises a second dopant level.

36. The method according to claim 35, wherein forming the first transistor and forming the second transistor comprise forming a gate material over a plurality of fins comprised of semiconductor material, masking the gate material of the first transistor, and implanting a dopant species into the gate material of the second transistor.

37. The method according to claim 36, wherein implanting the dopant species into the gate material of the second transistor comprises implanting the dopant species at an angle.

38. The method according to claim 37, wherein each of the plurality of fins comprises a first sidewall and a second sidewall opposing the first sidewall, wherein implanting the dopant species of the gate material of the second transistor comprises implanting the dopant species onto a first sidewall of the plurality of fins, but not the second sidewall of the plurality of fins.

39. The method according to claim 37, further comprising rotating the semiconductor device and repeating implanting the dopant species at the angle.

40. The method according to claim 36, wherein implanting the dopant species into the gate material of the second transistor comprises implanting Si, B, As, P, C, Ge, Sb, or combinations thereof.

41. The method according to claim 36, further comprising, before implanting the dopant species into the gate material, forming a source region and a drain region in each of the plurality of fins by implanting the dopant species into the plurality of fins, wherein implanting the dopant species into the plurality of fins comprises a first dose of the dopant species and a first energy level, wherein implanting the dopant species into the gate material comprises a second dose of the dopant species and a second energy level, wherein the second dose of the dopant species is less than the first dose of the dopant species, and wherein the second energy level is less than the first energy level.