Multiple independent serial link memory

• US 20070076479A1
• Filed: 12/30/2005
• Published: 04/05/2007
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki, Pyeon, Hong
• Granted Patent: US 7,652,922 B2
• Time in Patent Office: Days
• US Class Current: 365/185.110
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Claims

1. A semiconductor memory device comprising:

a plurality of memory banks;

a plurality of serial data link interfaces; and

a control module that controls data transfer between any one of the plurality of serial data link interfaces and any one of the plurality of memory banks.

2. The semiconductor memory device of claim 1, wherein the memory banks comprises non-volatile memory banks.

3. The semiconductor memory device of claim 2, wherein the non-volatile memory banks are flash memory banks.

4. The semiconductor memory device of claim 3, wherein the flash memory banks comprise serially connected transistor memory cells.

5. The semiconductor memory device of claim 4, wherein the flash memory banks comprise parallel connected transistor memory cells.

6. The semiconductor memory device of claim 1, wherein the control module receives computer-executable instructions to control the transfer of serial input and output data to and from one of the plurality of memory banks.

7. The semiconductor memory device of claim 6, wherein the control module controls the transfer of the serial input data in response to address information contained in an address field of the serial input data.

8. The semiconductor memory device of claim 1, wherein the plurality of memory banks, the plurality of serial data link interfaces and the control module are located within a single package having a one-side pad architecture.

9. The semiconductor memory device of claim 1, wherein the plurality of serial data link interfaces comprises two serial data link interfaces.

10. The semiconductor memory device of claim 1, wherein the plurality of serial data link interfaces comprises four serial data link interfaces.

11. The semiconductor memory device of claim 1, wherein the control module is configured to control simultaneous data transfer between at least two of the plurality of memory banks and at least two of the plurality of serial data link interfaces.

12. The semiconductor memory device of claim 1, wherein the device simultaneously performs a read operation in one of the plurality of memory banks through one of the serial data link interfaces, and a write operation in another of the plurality of memory banks through another of the plurality of serial data link interfaces.

13. A semiconductor memory device comprising:

a plurality of memory banks;

a plurality of serial data link interfaces for transferring data into and out of the memory device; and

a control module for independently controlling data transfer between any one of the plurality of serial data link interfaces and any one of the plurality of memory banks.

14. A semiconductor memory device comprising:

a plurality of memory banks;

a serial data link interface; and

a control module that controls data transfer between one of the plurality of serial data link interfaces and any one of the plurality of memory banks.

15. A semiconductor memory device comprising:

a plurality of memory banks;

a plurality of serial data link interfaces; and

a control module that processes multiple instructions to control data transfer between a selected one of the plurality serial data link interface and the plurality of memory banks.

16. The semiconductor memory device of claim 15, wherein the memory banks comprises non-volatile memory banks.

17. The semiconductor memory device of claim 16, wherein the non-volatile memory banks are flash memory banks.

18. The semiconductor memory device of claim 16, wherein the flash memory banks comprise serially connected transistor memory cells.

19. The semiconductor memory device of claim 16, wherein the flash memory banks comprise parallel connected transistor memory cells.

20. The semiconductor memory device of claim 15, wherein the control module is programmed with computer-executable instructions to parse an address field of incoming data and to control the transfer of the data to one of the plurality of memory banks identified in the address field.

21. The semiconductor memory device of claim 15, wherein the plurality of memory banks, the plurality of serial data link interfaces and the control module are located within a single package having a one-side pad architecture.

22. The semiconductor memory device of claim 15, wherein the control module is configured to simultaneously access at least two of the plurality of memory banks.

23. A method of controlling data transfer between a plurality of serial link interfaces and a plurality of memory banks in a semiconductor memory device, the method comprising:

(a) receiving a first data stream at a first of the plurality of serial data link interfaces;

(b) updating a serial data link interface status indicator corresponding to the first serial data link interface to indicate that the first serial data link interface is being utilized;

(c) parsing the first data stream to extract a first memory bank identifier;

(d) updating a memory bank status indicator corresponding to the first memory bank to indicate that the first memory bank is being utilized; and

(e) routing data between the first serial data link interface and the first memory bank.

24. The method of claim 23, wherein (c) comprises setting a bit value in a status register.

25. The method of claim 23, further including, after (e) updating the first memory bank status indicator to indicate that the first memory bank is no longer being utilized.

26. The method of claim 23, further comprising:

(f) receiving a second data stream at a second one of the plurality of serial data link interfaces;

(g) updating a serial data link interface status indicator corresponding to the second data link interface to indicate that the second serial data link interface is being utilized;

(h) parsing the second data stream to extract a second memory bank identifier;

(i) updating a memory bank status indicator corresponding to the second memory bank identifier to indicate that the second memory bank is being utilized; and

(j) during a time period that at least overlaps with a time period that (e) is performed, routing data between the second serial data link interface and the second memory bank.

27. The method of claim 23, further comprising:

(f) receiving from a second one of the plurality of serial data link interfaces a request for data stored in a second memory bank;

(g) updating a serial data link interface status indicator corresponding to the second data link interface to indicate that the second serial data link interface is being utilized;

(h) updating a memory bank status indicator corresponding to the second memory bank identifier to indicate that the second memory bank is being utilized; and

(i) during a time period that at least overlaps with a time period that (e) is performed, routing data between the second memory bank and the second serial data link interface.

28. A method of controlling the transfer of data between a serial data link interface and a plurality of memory banks in a semiconductor memory device, the method comprising:

(a) receiving a data stream at a serial data link interface;

(b) parsing the data stream to extract a first memory bank identifier;

(c) updating a first memory bank status indicator corresponding to the first memory bank to indicate that the first memory bank is being utilized; and

(d) routing data between the serial data link and the first memory bank.

29. The method of claim 28, wherein (c) comprises setting a bit value in a status register.

30. The method of claim 28, further including, after (d) updating the memory bank status indicator to indicate that the memory bank is no longer being utilized.

31. The method of claim 28, further comprising:

(e) receiving a second data stream at the serial link interfaces;

(f) parsing the second data stream to extract a second memory bank identifier;

(i) updating a memory bank status indicator corresponding to the second memory bank identifier to indicate that the second memory bank is being utilized; and

(j) during a time period that at least overlaps with a time period that (d) is performed, routing data between the serial link interface and the second memory bank.

32. The method of claim 28, wherein (d) and (j) are performed using separate processing threads.

33. The method of claim 28, further comprising:

(e) receiving from the serial link interface a request for data stored in a second memory bank;

(f) updating a memory bank status indicator corresponding to the second memory bank to indicate that the second memory bank is being utilized; and

(g) during a time period that at least overlaps with a time period that (d) is performed, routing data between the second memory bank and the serial link interface.

34. The method of claim 33, wherein (d) and (g) are performed using separate processing threads.

35. A flash memory system having a plurality of serially connected flash memory devices comprising:

a first flash memory device having a plurality of data input ports, a plurality of data output ports, a plurality of control input ports, and a plurality of control output ports, wherein the first flash memory device is receiving data and control signals from an external source; and

a second flash memory device having a plurality of data input ports, a plurality of data output ports, a plurality of control input ports, and a plurality of control output ports, wherein the second flash memory device is receiving data and control signals from a first flash memory device of the plurality of serially connected flash memory devices,

wherein the second flash memory device is providing data and control signals to the external source.

36. The flash memory system of claim 35, wherein the first flash memory device includes a plurality of control output ports for echoing values received by the first flash memory device to a second flash memory device.

37. The flash memory system of claim 36, wherein the external source is a memory controller.

38. The flash memory system of claim 37, wherein a single clock signal is communicated to each of the plurality of serially connected flash memory devices, and the output of the flash memory system is delayed by a predetermined latency.

39. The flash memory system of claim 35, wherein the plurality of serially connected flash memory devices are further comprising:

a plurality of flash memory banks;

a plurality of serial data link interfaces; and

a control module that controls data transfer between any one of the plurality of serial data link interfaces and any one of the plurality of memory banks,

wherein the control module is configured to control concurrent data transfer between at least two of the plurality of memory banks and at least two of the plurality of serial data link interfaces, and

wherein data is transferred in each of the plurality of serially connected flash memory devices using virtual multiple link.