Semiconductor device having first and second separation trenches

• US 20070090458A1
• Filed: 10/26/2006
• Published: 04/26/2007
• Est. Priority Date: 10/26/2005
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Yamada, Akira, Suzuki, Tomohisa, Muramoto, Hidetoshi
• Granted Patent: US 7,462,913 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A semiconductor device includes: a SOI substrate having a SOI layer, a buried oxide layer and a support substrate; multiple first separation trenches on the SOI layer; multiple MOS transistors, each of which is surrounded with one first separation trench; a second separation trench on the SOI layer including n-ply field trenches; and multiple field regions such that a k-th field region is surrounded with a k-th field trench. One MOS transistor is disposed in each field region. The MOS transistors are connected in series. The first MOS transistor has a gate terminal as an input terminal. The n-th MOS transistor is connected to the power source potential through an output resistor. The n-th field region has an electric potential, which is fixed to the power source potential.

Claims

1. A semiconductor device comprising:

a SOI substrate having a SOI layer, a buried oxide layer and a support substrate, which are stacked in this order;

a plurality of first separation trenches disposed on the SOI layer and reaching the buried oxide layer;

a plurality of MOS transistors, each of which is surrounded with one of the first separation trenches so that the MOS transistor is isolated;

a second separation trench disposed on the SOI layer and reaching the buried oxide layer, wherein the second separation trench includes a plurality of field trenches, which are defined as first to n-th field trenches so that the second separation trench provides n-ply field trenches, and wherein n represents a predetermined natural number; and

a plurality of field regions surrounded with the second separation trench, wherein the field regions are defined as first to n-th field regions so that a k-th field region is surrounded with a k-th field trench, and wherein k is a natural number in a range between 1 and n, wherein

one of the MOS transistors surrounded with one of the first separation trenches is disposed in each field region so that a k-th MOS transistor is disposed in the k-th field region,

the MOS transistors are electrically connected in series between a ground potential and a predetermined power source potential,

the first field region is disposed on an utmost outside and on a ground potential side, and the n-th field region is disposed on an utmost inside and on a power source potential side,

the first MOS transistor in the first field region has a gate terminal, which provides an input terminal,

the n-th MOS transistor in the n-th field region is electrically connected to the power source potential through an output resistor so that an output signal is retrieved from a connection between the n-th MOS transistor and the output resistor, and

the n-th field region has an electric potential, which is fixed to the power source potential.

2. The device according to claim 1, wherein

the first field region has an electric potential, which is fixed to the ground potential.

3. The device according to claim 1, further comprising:

a plurality of hollows disposed in the support substrate, wherein

each hollow reaches the buried oxide layer, and faces the field region through the buried oxide layer.

4. The device according to claim 1, further comprising:

a hollow disposed in a part of the support substrate, the part which faces all field regions through the buried oxide layer, wherein the hollow reaches the buried oxide layer.

5. The device according to claim 1, further comprising:

a plurality of third trenches disposed in the support substrate, wherein

each third trench reaches the buried oxide layer, and

each third trench surrounds a part of the support substrate, the part which fasces the field region through the buried oxide layer.

6. The device according to claim 5, wherein

each third trench faces the field trench through the buried oxide layer so that the third trenches have a same planar pattern as the field trenches.

7. The device according to claim 1, wherein

the support substrate is made of silicon.

8. The device according to claim 1, wherein

the support substrate is made of resistance material other than silicon.

9. The device according to claim 8, wherein

the support substrate has a resistance between a part of the support substrate and an adjacent part of the support substrate,

the part of the support substrate faces one field region, and the adjacent part of the support substrate faces adjacent one field region, and

the resistance of the support substrate is equal to or larger than 100 kΩ

.

10. The device according to claim 1, wherein

the buried oxide layer includes a first buried oxide film and a second buried oxide film,

the first buried oxide film faces the n-th field region,

the second buried oxide film faces other field regions,

the first buried oxide film has a relative dielectric constant smaller than that of the second buried oxide film.

11. The device according to claim 10, wherein

the buried oxide layer is made of silicon oxide,

the first buried oxide film is made of nano-crystal oxide silicon, carbon including oxide silicon or fluorine including oxide silicon.

12. The device according to claim 10, wherein

the first buried oxide film is a porous film.

13. The device according to claim 10, wherein

the first field region has an electric potential, which is fixed to the ground potential.

14. The device according to claim 10, wherein

each MOS transistor has a same breakdown voltage.

15. The device according to claim 1, further comprising:

a ground reference gate drive circuit having a ground potential as a reference potential; and

a floating reference gate drive circuit having a floating potential as a reference potential, wherein

the floating potential is the power source potential,

the SOI substrate, the first separation trenches, the MOS transistors, the second separation trench and the field regions provide a level shift circuit,

the level shift circuit shifts a level of an input/output signal between the ground potential and the floating potential, and

the ground reference gate drive circuit, the floating reference gate drive circuit and the level shift circuit provide a high voltage IC for driving an inverter.

16. The device according to claim 15, wherein

the inverter is disposed in an in-vehicle motor.

17. The device according to claim 15, wherein

the inverter is disposed in an in-vehicle air-conditioner.

18. A semiconductor device comprising:

a SOI substrate having a SOI layer, a buried oxide layer and a support substrate, which are stacked in this order;

a plurality of first separation trenches disposed on the SOI layer and reaching the buried oxide layer;

a plurality of MOS transistors, each of which is surrounded with one of the first separation trenches so that the MOS transistor is isolated;

a second separation trench disposed on the SOI layer and reaching the buried oxide layer, wherein the second separation trench includes a plurality of field trenches, which are defined as first to n-th field trenches so that the second separation trench provides n-ply field trenches, and wherein n represents a predetermined natural number;

a plurality of field regions surrounded with the second separation trench, wherein the field regions are defined as first to n-th field regions so that a k-th field region is surrounded with a k-th field trench, and wherein k is a natural number in a range between 1 and n; and

a hollow disposed in a part of the support substrate, the part which faces all field regions through the buried oxide layer, wherein

one of the MOS transistors surrounded with one of the first separation trenches is disposed in each field region so that a k-th MOS transistor is disposed in the k-th field region,

the MOS transistors are electrically connected in series between a ground potential and a predetermined power source potential,

the first field region is disposed on an utmost outside and on a ground potential side, and the n-th field region is disposed on an utmost inside and on a power source potential side,

the first MOS transistor in the first field region has a gate terminal, which provides an input terminal,

the n-th MOS transistor in the n-th field region is electrically connected to the power source potential through an output resistor so that an output signal is retrieved from a connection between the n-th MOS transistor and the output resistor, and

the hollow reaches the buried oxide layer.

19. The device according to claim 18, wherein

each MOS transistor has a same breakdown voltage.

20. The device according to claim 18, further comprising:

a ground reference gate drive circuit having a ground potential as a reference potential; and

a floating reference gate drive circuit having a floating potential as a reference potential, wherein

the floating potential is the power source potential,

the SOI substrate, the first separation trenches, the MOS transistors, the second separation trench and the field regions provide a level shift circuit,

the level shift circuit shifts a level of an input/output signal between the ground potential and the floating potential, and

the ground reference gate drive circuit, the floating reference gate drive circuit and the level shift circuit provide a high voltage IC for driving an inverter.

21. A semiconductor device comprising:

a SOI substrate having a SOI layer and an insulation substrate, which are stacked in this order;

a plurality of first separation trenches disposed on the SOI layer and reaching the insulation substrate;

a plurality of MOS transistors, each of which is surrounded with one of the first separation trenches so that the MOS transistor is isolated;

a second separation trench disposed on the SOI layer and reaching the insulation substrate, wherein the second separation trench includes a plurality of field trenches, which are defined as first to n-th field trenches so that the second separation trench provides n-ply field trenches, and wherein n represents a predetermined natural number; and

a plurality of field regions surrounded with the second separation trench, wherein the field regions are defined as first to n-th field regions so that a k-th field region is surrounded with a k-th field trench, and wherein k is a natural number in a range between 1 and n, wherein

one of the MOS transistors surrounded with one of the first separation trenches is disposed in each field region so that a k-th MOS transistor is disposed in the k-th field region,

the MOS transistors are electrically connected in series between a ground potential and a predetermined power source potential,

the first field region is disposed on an utmost outside and on a ground potential side, and the n-th field region is disposed on an utmost inside and on a power source potential side,

the first MOS transistor in the first field region has a gate terminal, which provides an input terminal, and

the n-th MOS transistor in the n-th field region is electrically connected to the power source potential through an output resistor so that an output signal is retrieved from a connection between the n-th MOS transistor and the output resistor.

22. The device according to claim 21, wherein

the n-th field region has an electric potential, which is fixed to the power source potential.

23. The device according to claim 21, wherein

each MOS transistor has a same breakdown voltage.

24. The device according to claim 21, further comprising:

a ground reference gate drive circuit having a ground potential as a reference potential; and

a floating reference gate drive circuit having a floating potential as a reference potential, wherein

the floating potential is the power source potential,

the SOI substrate, the first separation trenches, the MOS transistors, the second separation trench and the field regions provide a level shift circuit,

the level shift circuit shifts a level of an input/output signal between the ground potential and the floating potential, and

the ground reference gate drive circuit, the floating reference gate drive circuit and the level shift circuit provide a high voltage IC for driving an inverter.

25. A semiconductor device comprising:

a SOI substrate having a SOI layer, a buried oxide layer and a support substrate, which are stacked in this order;

a plurality of first separation trenches disposed on the SOI layer and reaching the buried oxide layer;

a plurality of MOS transistors, each of which is surrounded with one of the first separation trenches so that the MOS transistor is isolated;

a second separation trench disposed on the SOI layer and reaching the buried oxide layer, wherein the second separation trench includes a plurality of field trenches, which are defined as first to n-th field trenches so that the second separation trench provides n-ply field trenches, and wherein n represents a predetermined natural number; and

a plurality of field regions surrounded with the second separation trench, wherein the field regions are defined as first to n-th field regions so that a k-th field region is surrounded with a k-th field trench, and wherein k is a natural number in a range between 1 and n, wherein

one of the MOS transistors surrounded with one of the first separation trenches is disposed in each field region so that a k-th MOS transistor is disposed in the k-th field region,

the MOS transistors are electrically connected in series between a ground potential and a predetermined power source potential,

the first field region is disposed on an utmost outside and on a ground potential side, and the n-th field region is disposed on an utmost inside and on a power source potential side,

the first MOS transistor in the first field region has a gate terminal, which provides an input terminal,

the n-th MOS transistor in the n-th field region is electrically connected to the power source potential through an output resistor so that an output signal is retrieved from a connection between the n-th MOS transistor and the output resistor, and

the buried oxide layer has a relative dielectric constant smaller than 3.9.

26. The device according to claim 25, wherein

the buried oxide layer has a relative dielectric constant smaller than 2.0.

27. The device according to claim 25, wherein

the buried oxide layer is made of nano-crystal oxide silicon, carbon including oxide silicon or fluorine including oxide silicon.

28. The device according to claim 25, wherein

the buried oxide layer is a porous film.

29. The device according to claim 25, wherein

the n-th field region has an electric potential, which is fixed to the power source potential.

30. The device according to claim 25, wherein

each MOS transistor has a same breakdown voltage.

31. The device according to claim 25, further comprising:

a ground reference gate drive circuit having a ground potential as a reference potential; and

a floating reference gate drive circuit having a floating potential as a reference potential, wherein

the floating potential is the power source potential,

the SOI substrate, the first separation trenches, the MOS transistors, the second separation trench and the field regions provide a level shift circuit,

the level shift circuit shifts a level of an input/output signal between the ground potential and the floating potential, and

the ground reference gate drive circuit, the floating reference gate drive circuit and the level shift circuit provide a high voltage IC for driving an inverter.