Embedded inductor and application thereof

• US 20070090912A1
• Filed: 05/30/2006
• Published: 04/26/2007
• Est. Priority Date: 10/20/2005
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Lee, Sheng-Yuan
• Granted Patent: US 7,339,452 B2
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 1/165 : incorporating printed inductors
• CPC Class Codes: H05K 2201/09672 : Superposed layout, i.e. in different planes parallel traces in one plane H05K2201/09236

Abstract

An embedded inductor suitable for a wiring board is provided. The wiring board having a plurality of patterned conductive layers and a plurality of insulating layers, and one of the insulating layers is disposed between any two adjacent of the patterned conductive layers. The embedded inductor at least includes a first conductive trace, a second conductive trace, a third conductive trace, a first conductive structure, and a second conductive structure. These conductive traces are respectively formed of different patterned conductive layers of the wiring board. The first conductive structure and the second conductive structure passing through the insulating layers connect the conductive traces in a spiral pattern. The embedded inductor with such spiral pattern is arranged on a plane that is perpendicular to the patterned conductive layers of the wiring board.

Claims

1. An embedded inductor suitable for applying in a wiring board, comprising:

a first conductive trace in a first patterned conductive layer of the wiring board;

a second conductive trace in a second patterned conductive layer of the wiring board;

a third conductive trace in a third patterned conductive layer of the wiring board;

a first conductive structure electrically connecting the first conductive trace and the second conductive trace; and

a second conductive structure electrically connecting the second conductive trace and the third conductive trace;

wherein the first conductive trace, the second conductive trace, the third conductive trace, the first conductive structure, and the second conductive structure are arranged spirally on a plane.

2. The embedded inductor of claim 1, wherein the wiring board further comprises a first insulating layer disposed between the first patterned conductive layer and the third patterned conductive layer, and a second insulating layer disposed between the second patterned conductive layer and the third patterned conductive layer.

3. The embedded inductor of claim 2, wherein the third patterned conductive layer is disposed between the first patterned conductive layer and the second patterned conductive layer.

4. The embedded inductor of claim 2, wherein the first conductive structure passes through the first patterned conductive layer, the second patterned conductive layer, the third patterned conductive layer, the first insulating layer, and the second insulating layer.

5. The embedded inductor of claim 2, wherein the second conductive structure passes through the second patterned conductive layer, the third patterned conductive layer, and the second insulating layer.

6. The embedded inductor of claim 1, wherein the plane is perpendicular to the first patterned conductive layer.

7. The embedded inductor of claim 1, further comprising:

a fourth conductive trace formed of a fourth patterned conductive layer of the wiring board; and

a third conductive structure electrically connected to the third conductive trace and the fourth conductive trace.

8. The embedded inductor of claim 7, further comprising:

a fifth conductive trace formed of a fifth patterned conductive layer of the wiring board; and

a fourth conductive structure passing through the wiring board and electrically connected to the fourth conductive trace and the fifth conductive trace.

9. The embedded inductor of claim 1, wherein the first conductive structure is either a conductive via or a plating through hole.

10. The embedded inductor of claim 1, wherein the wiring board is either a circuit board or a package substrate.

11. A chip package, comprising:

a substrate comprising;

a first patterned conductive layer having a first conductive trace;

a second patterned conductive layer having a second conductive trace;

a third patterned conductive layer having a third conductive trace;

a first conductive structure electrically connecting the first conductive trace and the second conductive trace; and

a second conductive structure electrically connecting the second conductive trace and the third conductive trace;

wherein the first conductive trace, the second conductive trace, the third conductive trace, the first conductive structure, and the second conductive structure are arranged spirally on a plane;

a chip loaded on the substrate, wherein the chip comprises a plurality of connection structures; and

an insulating material covering the connection structures of the chip.

12. The chip package of claim 11, wherein the substrate further comprises a first insulating layer disposed between the first patterned conductive layer and the third patterned conductive layer, and a second insulating layer disposed between the second patterned conductive layer and the third patterned conductive layer.

13. The chip package of claim 12, wherein the third patterned conductive layer is disposed between the first patterned conductive layer and the second patterned conductive layer.

14. The chip package of claim 12, wherein the first conductive structure passes through the first patterned conductive layer, the second patterned conductive layer, the third patterned conductive layer, the first insulating layer, and the second insulating layer.

15. The chip package of claim 12, wherein the second conductive structure passes through the second patterned conductive layer, the third patterned conductive layer, and the second insulating layer.

16. The chip package of claim 11, wherein the plane is perpendicular to the surface of the substrate.

17. The chip package of claim 11, wherein the substrate further comprises:

a fourth patterned conductive layer having a fourth conductive trace; and

a third conductive structure electrically connected to the third conductive trace and the fourth conductive trace.

18. The chip package of claim 11, wherein the first conductive structure is either a conductive via or a plating through hole.

19. The chip package of claim 11, wherein the connection structures of the chip are a plurality of bonding wires.

20. The chip package of claim 11, wherein the connection structures of the chip are a plurality of conductive bumps.