Semiconductor chip with post-passivation scheme formed over passivation layer

• US 20070096313A1
• Filed: 10/28/2005
• Published: 05/03/2007
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming, Lo, Hsin-Jung, Lin, Ching-San
• Granted Patent: US 7,397,121 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05173 Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/05176 Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05673 Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/05676 Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13169 : Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/13173 : Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/13176 : Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/4554 : Coating
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48477 : being a pre-ball (i.e. a ball formed by capillary bonding)
• CPC Class Codes: H01L 2224/4943 : the connecting portions being staggered
• CPC Class Codes: H01L 2224/85051 : Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns

Claims

1. A semiconductor chip, comprising:

a semiconductor substrate comprising a peripherial region having no semiconductor devices, and a center region having multiple semiconductor devices;

an interconnecting structure over said semiconductor substrate;

a passivation layer over said first interconnecting structure, an opening in said passivation layer exposing a first contact pad of said first interconnecting structure, wherein said first contact pad is over said peripherial region;

a second interconnecting structure over said passivation layer, said second interconnecting structure comprises a second contact pad connected to said first contact pad, wherein the position of said second contact pad from a top view is different from that of said first contact pad; and

a metal bump on said second contact pad and over said multiple semiconductor devices, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

2. The semiconductor chip of claim 1 further comprising a polymer layer over said passivation layer, wherein said second pad is on said polymer layer.

3. A semiconductor chip, comprising:

a semiconductor substrate;

a first interconnecting structure over said semiconductor substrate;

a passivation layer over said first interconnecting structure, multiple openings in said passivation layer exposing multiple first and second contact pads of said first interconnecting structure, wherein said first and second contact pads are lined along an edge of said semiconductor chip, and one of said first contact pads is between the neighboring two of said second contact pads; and

a second interconnecting structure over said passivation layer and said first and second contact pads, wherein said second interconnecting structure comprising multiple third contact pads connected to said multiple first contact pads, and multiple fourth contact pads over said multiple second contact pads, and wherein the position of said multiple third contact pads from a top view is different from that of said multiple first contact pads.

4. The semiconductor chip of claim 3 further comprising multiple bumps on said third contact pads.

5. The semiconductor chip of claim 3 further comprising multiple bumps on said fourth contact pads.

6. The semiconductor chip of claim 3, wherein said third contact pads are used to be wirebonded thereto.

7. The semiconductor chip of claim 3, wherein said fourth contact pads are used to be wirebonded thereto.

8. The semiconductor chip of claim 3, wherein said semiconductor substrate comprises multiple MOS devices under said first and second contact pads.

9. The semiconductor chip of claim 3, wherein said semiconductor substrate comprises a peripherial region having no semiconductor devices, and a center region having multiple semiconductor devices, and said first and second contact pads are over said peripherial region.

10. The semiconductor chip of claim 3 further comprising a polymer layer over said passivation layer, wherein said multiple third contact pads are on said polymer layer.

11. A semiconductor chip, comprising:

a semiconductor substrate;

an interconnecting structure over said semiconductor substrate;

a passivation layer over said first interconnecting structure, multiple openings in said passivation layer exposing multiple first and second contact pads of said first interconnecting structure, wherein said first and second contact pads are lined along an edge of said semiconductor chip, and one of said first contact pads is between the neighboring two of said second contact pads;

a second interconnecting structure over said passivation layer, wherein said second interconnecting structure comprising multiple third contact pads connected to said multiple first contact pads, and multiple fourth contact pads connected to said multiple second contact pads, and wherein the position of said multiple third contact pads from a top view is different from that of said multiple first contact pads, and said multiple third contact pads are aligned in a line, and wherein the position of said multiple fourth contact pads from a top view is different from that of said multiple second contact pads, and said multiple fourth contact pads are aligned in another line.

12. The semiconductor chip of claim 11 further comprising multiple bumps on said third contact pads.

13. The semiconductor chip of claim 12, wherein said fourth contact pads are used to be wirebonded thereto.

14. The semiconductor chip of claim 11, wherein said third contact pads are used to be wirebonded thereto.

15. The semiconductor chip of claim 11, wherein said semiconductor substrate comprises multiple MOS devices under said first and second contact pads.

16. The semiconductor chip of claim 11, wherein said semiconductor substrate comprises a peripherial region having no semiconductor devices, and a center region having multiple semiconductor devices, and said first and second contact pads are over said peripherial region.

17. The semiconductor chip of claim 11 further comprising a polymer layer over said passivation layer, wherein said multiple third and fourth contact pads are on said polymer layer.