Power reducing logic and non-destructive latch circuits and applications

• US 20070103201A1
• Filed: 11/10/2005
• Published: 05/10/2007
• Est. Priority Date: 11/10/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Siers, Scott, Liyanage, Ruchira, Lau, Hon
• Granted Patent: US 8,421,502 B2
• Time in Patent Office: Days
• US Class Current: 326/93
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.

Claims

1. A chip, comprising:

a logic circuit having a plurality of gates with gate inputs and one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode.

2. The chip of claim 1, in which the logic circuit comprises one or more sequential logic circuits.

3. The chip of claim 1, in which the latches comprise non-destructive latch circuits.

4. The chip of claim 3, in which the non-destructive latch circuits comprise non-destructive R and S latches.

5. A chip, comprising:

a latch circuit having an output gate with a first input coupled to a latch data node and a second input coupled to a signal to cause the gate to provide a known output value.

6. The chip of claim 5, in which the latch circuit is a set latch circuit.

7. The chip of claim 6, in which the output gate comprises a NANDE gate.

8. The chip of claim 7, in which the latch circuit comprises a passgate coupled between a latch input and the latch data node.

9. The chip of claim 8, in which the latch circuit comprises a cross-coupled pair of inverters coupled to the latch output node.

10. The chip of claim 9, in which the cross-coupled pair of inverters comprises a tri-stateable inverter with its output coupled to the latch output node.

11. A chip, comprising:

a latch circuit comprising;

a restore circuit coupled to a latch data node, and

an inverter coupled to the latch data node, the inverter having an output to provide an output for the latch circuit.

12. The chip of claim 11, in which the latch circuit comprises a tri-stateable inverter coupled to the latch data node, the tri-stateable inverter to be controllably disabled when a sleep mode is entered.

13. The chip of claim 12, in which the latch circuit comprises a transistor to controllably provide to the tri-stateable inverter a supply when not in the sleep mode.

14. The chip of claim 13, in which the latch circuit is a set latch circuit comprising a transistor coupled between a low supply reference and the latch data node to pull down the latch data node to a low state when the sleep mode is entered.

15. The chip of claim 14, in which the restore circuit comprises a pair of NOR gates to store the value from the latch data node when the sleep mode is entered.

16. The chip of claim 14, in which the latch circuit is a reset latch circuit comprising a transistor coupled between a high supply reference and the latch data node to pull up the latch data node to a high state when the sleep mode is entered.

17. The chip of claim 16, in which the restore circuit comprises a pair of NAND gates to store the value from the latch data node when the sleep mode is entered.

18. A system, comprising:

(a) a microprocessor comprising a logic circuit having;

(i) a plurality of gates with gate inputs, and

(ii) one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode;

(b) an antenna; and

(c) a wireless interface coupled to the microprocessor and to the antenna to communicatively link the microprocessor to a wireless network.

19. The system of claim 18, in which the logic circuit comprises one or more sequential logic circuits.

20. The system of claim 18, in which the latches comprise non-destructive latch circuits.

21. The chip of claim 20, in which the non-destructive latch circuits comprise non-destructive R and S latches.