CAPACITOR CHARGING METHODS AND APPARATUS

• US 20070103943A1
• Filed: 12/19/2006
• Published: 05/10/2007
• Est. Priority Date: 05/09/2005
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Humenick, John, Tsai, Tseng-Nan, Lee, Nai-Chi, Mangtani, Vijay
• Granted Patent: US 7,787,262 B2
• Time in Patent Office: Days
• US Class Current: 363/20
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence

Abstract

A capacitor charging circuit is provided with a primary side output voltage sensing circuit including an RC network having an RC time constant with a predetermined relationship to the RC time constant of the output capacitor. Once the capacitor voltage reaches a fully charged level, the charging mode is terminated. The output voltage is continuously detected by measuring the voltage across the primary side RC network that decays at a predetermined rate with respect to the output capacitor and the charging mode is commenced once the RC voltage falls to a predetermined level. According to a further aspect of the invention, a switch control circuit in a flyback converter controls the switch off time in response to detection of a change in the slope polarity of the voltage at a terminal of the switch.

Claims

1. In a capacitor charging circuit having a transformer with a primary winding coupled to a switch and a secondary winding coupled to an output capacitor, apparatus comprising:

an RC network on a primary side of the transformer associated with the primary winding and having an RC time constant with a predetermined relationship to an RC time constant associated with the output capacitor, and wherein a regulation voltage is provided across the RC network; and

a control circuit responsive to the regulation voltage for providing an enable signal to enable a charging mode during which the switch is turned on and off to charge the output capacitor and to disable the charging mode.

2. The apparatus of claim 1 wherein the RC time constant of the RC network is substantially equal to the RC time constant associated with the output capacitor.

3. The apparatus of claim 1 wherein the RC time constant of the RC network is less than the RC time constant associated with the output capacitor.

4. The apparatus of claim 1 wherein the enable signal transitions from a first logic level to a second logic level to disable the charging mode when the regulation voltage exceeds a first predetermined level and wherein the enable signal transitions from the second logic level to the first logic level to enable the charging mode when the regulation voltage falls to below a second predetermined level, wherein the second predetermined level is less than the first predetermined level.

5. The apparatus of claim 1 further comprising an attenuator coupled to the primary winding to provide an attenuated voltage proportional to a voltage across the primary winding and a sample and hold circuit coupled between the attenuator and the RC network.

6. The apparatus of claim 5 wherein the control circuit comprises:

a first comparator having a first input coupled to an output of the sample and hold circuit, a second input responsive to a reference voltage, and an output at which is provided a full charge indicator signal at a first logic level when the output voltage is greater than a desired level and a second logic level when the output voltage is less than the desired level; and

a second comparator having a first input responsive to the regulation voltage, a second input responsive to a second reference voltage, and an output at which is provided a low charge indicator signal at a first logic level when the output voltage is greater than an unacceptable level and a second logic level when the output voltage is less than the unacceptable level.

7. The apparatus of claim 6 wherein the sample and hold circuit provides a sampled and held voltage and comprises a switch coupled between the attenuator and the RC network that conducts when the attenuated voltage is greater than the sampled and held voltage.

8. The apparatus of claim 5 wherein the control circuit comprises:

a first comparator having a first input coupled to an output of the attenuator, a second input responsive to a reference voltage, and an output at which is provided a full charge indicator signal at a first logic level when the output voltage is greater than the desired level and a second logic level when the output voltage is less than the desired level; and

a second comparator having a first input responsive to the regulation voltage, a second input responsive to a second reference voltage, and an output at which is provided an unacceptable charge indicator signal at a first logic level when the output voltage is greater than an unacceptable level and a second logic level when the output voltage is less than the unacceptable level.

9. The apparatus of claim 8 wherein the sample and hold circuit comprises:

a comparator having a first input responsive to the attenuated voltage, a second input responsive to the regulation voltage, and an output at which a comparator output signal is provided; and

a switch controlled by the comparator output signal to conduct and charge the RC network when the attenuated voltage is greater than the regulation voltage.

10. The apparatus of claim 1 further comprising an attenuator coupled to the primary winding to provide an attenuated voltage proportional to a voltage across the primary winding, wherein the control circuit comprises:

a first comparator having a first input coupled to an output of the attenuator, a second input responsive to a reference voltage, and an output at which is provided a full charge indicator signal at a first logic level when the output voltage is greater than the desired level and a second logic level when the output voltage is less than the desired level; and

a second comparator having a first input responsive to the regulation voltage, a second input responsive to a second reference voltage, and an output at which is provided an unacceptable charge indicator signal at a first logic level when the output voltage is greater than an unacceptable level and a second logic level when the output voltage is less than the unacceptable level.

11. The apparatus of claim 10 further comprising:

a voltage source providing a third reference voltage; and

a buffer having an input coupled to the voltage source and an output coupled to the RC network wherein the buffer is a tristate buffer that is responsive to the enable signal to couple the third reference voltage to the RC network when the charging mode is enabled and to decouple the third reference voltage from the RC network when the charging mode is disabled.

12. In a capacitor charging circuit having a transformer with a primary winding coupled to a switch and a secondary winding coupled to an output capacitor across which an output voltage is provided, a method for maintaining the output capacitor in a substantially fully-charged condition, comprising:

detecting the output voltage from the primary side of the transformer by measuring a voltage across an RC network that discharges at a rate that has a predetermined relationship to a rate of discharge of the output capacitor; and

commencing a charging mode of operation during which the switch is turned on and off to charge the output capacitor in response to the voltage across the RC network falling to a predetermined level.

13. The method of claim 12 further comprising terminating the charging mode of operation in response to the voltage across the RC network exceeding a second predetermined level, wherein the second predetermined level is greater than the first predetermined level.

14. A flyback converter comprising:

a transformer having a primary winding and a secondary winding;

a switch having a terminal coupled to the primary winding; and

a switch control circuit having a first circuit portion for controlling the on time of the switch and a second circuit portion for controlling the off time of the switch, wherein the second circuit portion comprises a slope detection circuit to detect a change in the polarity of the voltage at the switch terminal.

15. The converter of claim 14 wherein the slope detection circuit comprises:

a sensing switch coupled to the switch terminal and having a control terminal;

a clamp coupled to the control terminal;

a resistor coupled to the control terminal; and

a comparator coupled to the control terminal and providing a comparator output signal that transitions from a first logic level to a second logic level when the slope of the voltage at the switch terminal changes from a negative slope to a positive slope.

16. The converter of claim 15 wherein the switch is comprised of a plurality of switches and wherein the sensing switch is one of the plurality of switches.

17. The converter of claim 14 wherein the slope detection circuit comprises:

a capacitor having a first terminal coupled to the switch terminal and a second terminal;

a resistor coupled to the second terminal of the capacitor; and

a comparator coupled to the second terminal of the capacitor and providing a comparator output signal that transitions from a first logic level to a second logic level when the slope of the voltage at the switch terminal changes from a negative slope to a positive slope.

18. The converter of claim 17 further comprising a clamp coupled between the second terminal of the capacitor and ground.

19. The converter of claim 17 further comprising a flip-flop having a set input responsive to the comparator output signal and an output at which a switch control signal is provided, wherein the second circuit portion of the switch control circuit comprises:

a second resistor coupled to the switch; and

a second comparator having a first input coupled to the second resistor, a second input responsive to a reference voltage, and providing an output signal to a reset input of the flip-flop.

20. In a flyback converter having a transformer with a primary winding coupled to a switch and a secondary winding, a method comprising:

detecting of a change in the polarity of the slope of a voltage at a terminal of the switch; and

turning the switch on in response to the detection.

21. The method of claim 20 wherein detecting comprises:

providing a sense switch having a first terminal coupled to the switch terminal and having a second, control terminal;

clamping the voltage at the control terminal;

coupling a resistor to the control terminal;

comparing the voltage at the control terminal to a reference voltage to detect a change in the polarity of the slope of the voltage at switch terminal from a negative slope to a positive slope.

22. The method of claim 20 wherein detecting comprises:

providing a capacitor having a first terminal coupled to the switch terminal and having a second terminal;

coupling a resistor to the second terminal of the capacitor;

comparing the voltage at the second terminal of the capacitor to a reference voltage to detect a change in the polarity of the slope of the voltage at switch terminal from a negative slope to a positive slope.

23. The method of claim 22 further comprising clamping the voltage at the second terminal of the capacitor.

24. The method of claim 20 further comprising:

measuring a current in the primary winding to determine when the primary winding current exceeds a predetermined level; and

turning the switch off in response to the determination.