DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE

  • US 20070105299A1
  • Filed: 11/10/2005
  • Published: 05/10/2007
  • Est. Priority Date: 11/10/2005
  • Status: Active Grant
First Claim
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1. A method of providing a dual stress memory technique in a semiconductor device including an nFET and a pFET, the method comprising the steps of:

  • forming a first stress layer over the semiconductor device;

    forming an etch stop layer over the first stress layer;

    removing the first stress layer and the etch stop layer over a first one of the nFET and the pFET;

    forming a second stress layer over the semiconductor device, wherein a stress layer over the pFET includes a compressive stress silicon nitride;

    annealing to memorize stress in the semiconductor device; and

    removing the first and second stress layer and the etch stop layer.

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