Architecture for generating intermediate representations for program code conversion

• US 20070106983A1
• Filed: 11/06/2006
• Published: 05/10/2007
• Est. Priority Date: 05/02/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: Transitive Limited (International Business Machines Corporation)
• Inventors: Haikney, David, Owen, Daniel, Andrews, Jonathan, Howson, Miles
• Granted Patent: US 7,921,413 B2
• Time in Patent Office: Days
• US Class Current: 717/136
• CPC Class Codes: G06F 9/45516 Runtime code conversion or optimisation

Abstract

An improved architecture for a program code conversion apparatus and method for generating intermediate representations for program code conversion. The program code conversion apparatus determines which types of IR nodes to generate in an intermediate representation (IR) of subject code (10) to be translated. Depending upon the particular subject and target computing environments involved in the conversion, the program code conversion apparatus utilizes either base nodes, complex nodes, polymorphic nodes, and architecture specific nodes, or some combination thereof, in generating the intermediate representation.

Claims

1. A method of translating subject code of a subject architecture into target code of a target architecture, comprising the computer-implemented steps of:

decoding the subject code and generating an intermediate representation including a plurality of subject architecture specific nodes which are specific to the subject architecture;

converting the subject architecture specific nodes into target architecture specific nodes which are specific to the target architecture; and

generating target code from the intermediate representation including generating target code instructions from the target architecture specific nodes.

2. The method of claim 1, wherein at least one of the subject architecture specific nodes comprises a specialised conversion component which generates one or more corresponding target architecture specific nodes, wherein the specialised conversion component is specific to a subject architecture target architecture pair.

3. The method of claim 1, wherein at least one of the target architecture specific nodes comprises an implementation component which is invoked to generate a target code instruction from the target architecture specific node.

4. The method of claim 1, wherein each of the plurality of subject architecture specific nodes is associated with a respective instruction type in the subject architecture.

5. The method of claim 1, wherein each of the target architecture specific nodes is associated with a particular instruction type in the target architecture.

6. The method of claim 1, wherein the step of generating target code comprises generating one target code instruction from each respective target architecture specific node.

7. The method of claim 2, wherein at least one of the plurality of subject architecture specific nodes further comprises a data component representing semantics of a respective subject code instruction.

8. The method of claim 3, wherein at least one of the target architecture specific instructions further comprises a data component representing semantics of a respective target code instruction.

9. The method of claim 1, wherein the step of generating an intermediate representation further includes generating at least one base node which is generic to the subject architecture and the target architecture.

10. The method of claim 1, wherein:

the step of converting further comprises converting at least one of the subject architecture specific nodes into one or more base nodes which are generic to the subject architecture and the target architecture; and

the step of generating the target code further comprises generating target code instructions from the one or more base nodes.

11. The method of claim 10, wherein the at least one of the subject architecture specific nodes comprises a generic conversion component which generates the one or more base node.

12. The method of claim 1, further comprising the step of:

performing subject architecture specific optimisations of the plurality of subject architecture specific nodes.

13. The method of claim 1, further comprising the step of:

performing target architecture specific optimisations of the target architecture specific nodes.

14. A computer readable storage medium having translator software resident thereon in the form of computer readable code executable by a computer to perform the steps of:

decoding the subject code and generating an intermediate representation including a plurality of subject architecture specific nodes which are specific to the subject architecture;

converting the subject architecture specific nodes into target architecture specific nodes which are specific to the target architecture; and

generating target code from the intermediate representation including generating target code instructions from the target architecture specific nodes.

15. A translator apparatus for use in a target computing environment having a processor and a memory coupled to the processor for translating subject code capable of being executed on a subject architecture to target program code capable of being executed on the target architecture of the target computing environment using the translator apparatus, wherein the translator apparatus comprises:

a decoder unit arranged to decode the subject code and generate an intermediate representation including a plurality of subject architecture specific nodes which are specific to the subject architecture;

a converter unit arranged to convert the subject architecture specific nodes into target architecture specific nodes which are specific to the target architecture; and

a generator unit arranged to generate target code from the intermediate representation including generating target code instructions from the target architecture specific nodes.