Power Semiconductor Component With Charge Compensation Structure And Method For The Fabrication Thereof

• US 20070108512A1
• Filed: 10/25/2006
• Published: 05/17/2007
• Est. Priority Date: 10/25/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Schulze, Hans-Joachim, Strack, Helmut, Pfirsch, Frank, Mauder, Anton, Sedlmaier, Stefan, Willmeroth, Armin
• Granted Patent: US 7,554,137 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/2205 from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
• CPC Class Codes: H01L 21/2252 using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/298 Semiconductor material, e.g. amorphous silicon
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention relates to a power semiconductor component (1) with charge compensation structure (3) and a method for the fabrication thereof. For this purpose, the power semiconductor component (1) has a semiconductor body (4) having a drift path (5) between two electrodes (6, 7). The drift path (5) has drift zones of a first conduction type, which provide a current path between the electrodes (6, 7) in the drift path, while charge compensation zones (11) of a complementary conduction type constrict the current path of the drift path (5). For this purpose, the drift path (5) has two alternately arranged, epitaxially grown diffusion zone types (9, 10), the first drift zone type (9) having monocrystalline semiconductor material on a monocrystalline substrate (12), and a second drift zone type (10) having monocrystalline semiconductor material in a trench structure (13), with complementarily doped walls (14, 15), the complementarily doped walls (14, 15) forming the charge compensation zones (11).

Claims

1. A semiconductor component with charge compensation structure, comprising, in a semiconductor body, a drift path between two electrodes, and the drift path having drift zones of a first conduction type, which provide a current path between the electrodes in the drift path, and charge compensation zones of a complementary conduction type, which constrict the current path of the drift path, the drift zones comprising two alternately arranged, epitaxially grown drift zone types of the first conduction type, a first drift zone type having monocrystalline semiconductor material on a monocrystalline substrate, and a second drift zone type having monocrystalline semiconductor material in a trench structure with complementarily doped walls, the complementarily doped walls forming the charge compensation zones.

2. A semiconductor component according to claim 1,

wherein

the ratio v between the width b_K of the charge compensation zones transversely with respect to the current path and the width b_D of the drift zones transversely with respect to the current path is b_K/b_D=V≦

0.1.

3. A semiconductor component according to claim 2,

wherein

the width of the charge compensation zones is defined by the penetration depth of a dopant of the complementary conduction type into drift zone material of the first drift zone type, the penetration depth being arranged in wall regions of trench structures which are filled epitaxially with monocrystalline semiconductor material of the first conduction type and extend in the current path direction.

4. A semiconductor component according to claim 2,

wherein

the width of the charge compensation zones is defined by an epitaxial growth thickness of a monocrystalline semiconductor material layer of the complementary conduction type which is arranged on wall regions of trench structures which are filled epitaxially with monocrystalline semiconductor material of the first conduction type and extend in the current path direction.

5. A semiconductor component according to claim 1,

wherein

the charge compensation zones and the drift zones are arranged in strip-type fashion alongside one another between the electrodes.

6. A semiconductor component according to claim 5,

wherein

a respective strip-type drift zone is delimited in terms of its width transversely with respect to the current path by two strip-type charge compensation zones in the current path direction.

7. A semiconductor component according to claim 1,

wherein

the semiconductor body has a highly doped substrate of the first or of the complementary conduction type, on which is arranged a weakly doped to medium-doped epitaxial layer of the first conduction type with the drift path.

8. A semiconductor component according to claim 7,

wherein

the charge compensation zones extend in terms of their depth from a top side of the semiconductor body as far as a top side of the substrate.

9. A semiconductor component according to claim 1,

wherein

the semiconductor body has a nonpatterned weakly doped pedestal epitaxial layer of the first conduction type between the drift path and the substrate.

10. A semiconductor component according to claim 9,

wherein

the charge compensation zones extend in terms of their depth from a top side of the semiconductor body as far as a top side of the pedestal epitaxial layer.

11. A semiconductor component according to claim 1,

wherein

the semiconductor component has, in the region of the drift path transversely with respect to the current direction, a layer of the first conduction type which is doped by means of proton implantation and is doped more highly than the surrounding drift zones and has, in the region of the charge compensation zones, a reduced net concentration of the substitutional defects of the complementary conduction type.

12. A semiconductor component according to claim 1,

wherein

the first and/or the second drift zone type have a monocrystalline semiconductor material of the first conduction type, in which impurity atoms are arranged substitutionally and/or interstitially, said impurity atoms reducing the diffusion coefficient of the complementarily doping defects.

13. A semiconductor component according to claim 1,

wherein

the second drift zone type has a monocrystalline semiconductor material of the first conduction type in the trench structure provided with complementarily doped walls, a substitutionally and/or interstitially arranged carbon concentration [C] up to [C]≦

1×

10²⁰ cm<sup>−

3</sup>.

14. A semiconductor component according to claim 1,

wherein

the second drift zone type has a monocrystalline semiconductor material of the first conduction type in the trench structure provided with complementarily doped walls, the trench structure not being completely filled and having a termination filling of an insulation material, preferably an SiO₂ termination filling, in the upper region of the trenches.

15. A semiconductor component according to claim 1,

wherein

the complementarily doped walls of the trench structure have, toward the filling monocrystalline semiconductor material of the second drift zone type, a diffusion-inhibiting monocrystalline layer with Si_xGe_yC_z, where x>

y and x>

z, preferably with Si_0.86 Ge_0.07 C_0.07.

16. A semiconductor component according to claim 14,

wherein

germanium and carbon are arranged substitutionally on silicon crystal lattice sites.

17. A semiconductor component according to claim 1,

wherein

a diffusion-inhibiting layer is provided between the complementarily doped walls f the trench structure and the filling monocrystalline semiconductor material of the second drift zone type, said diffusion-inhibiting layer being arranged in the complementarily doped walls and/or in the filling semiconductor material.

18. A semiconductor component according to claim 17, wherein amorphous silicon or silicon carbide, in particular cubic silicon carbide, or silicon germanium being provided as the diffusion-inhibiting layer.

19. A semiconductor component according to claim 1,

wherein

the semiconductor component has an edge structure with at least one edge trench as edge termination.

20. A semiconductor component according to claim 19,

wherein

the edge structure has at least one complementarily doped edge compensation zone of a trench wall of the edge trench along the edge of the semiconductor component, the adjoining trench having, toward the edge of the semiconductor component, semiconductor material grown in monocrystalline fashion, it being possible for the complementarily doped edge compensation zone to be floating.

21. A semiconductor component according to claim 20,

wherein

the edge structure has an edge contour toward the edge of the semiconductor component, which edge contour, through isotropic and/or anisotropic etching of the epitaxial layer grown in the edge trench, has a curved contour that extends from the top side of the semiconductor body preferably right into the substrate in the region of the monocrystalline semiconductor material, an edge passivation layer adapted to the edge contour being arranged on the semiconductor layer.

22. A semiconductor component according to claim 21,

wherein

the edge passivation layer has a semiconductor oxide, a semiconductor nitride, a DLC, a thermally grown oxide and/or a silicon carbide.

23. A semiconductor component according to claim 19,

wherein

a semiconductor component without a charge compensation zone in a drift path has the edge structure with edge trench, edge compensation zone, which may be floating, and edge contour passivation.

64. A semiconductor component according to claim 1, wherein the semiconductor component is a power semiconductor component.

24. A method for fabricating semiconductor components, the method comprising the following method steps of:

providing a highly doped semiconductor wafer of a first or of a complementary conduction type having a multiplicity of semiconductor component positions, arranged in rows and columns, as a substrate of a semiconductor body;

growing an epitaxial layer of the first conduction type onto the semiconductor wafer as starting material for a first drift zone type;

introducing a trench structure in the semiconductor component positions;

doping the trench structure walls by means of a dopant layer of a complementary conduction type for charge compensation zones;

anisotropically etching free the bottom region of the trench structure and the top sides of the first drift zone types;

growing a medium-doped epitaxial layer of the first conduction type in the trench structure as starting material for a second drift zone type.

25. A method according to claim 24, further comprising the following additional steps of:

planarizing the top side of the semiconductor wafer as far as the grown drift zone types to form a semiconductor body with a planarized top side;

fabricating top side structures and rear side structures in and/or on the semiconductor body in order to complete the semiconductor components in the semiconductor component positions of the semiconductor wafer;

separating the semiconductor wafer into individual semiconductor components.

26. A method according to claim 24,

wherein

a weakly doped pedestal epitaxial layer of the first conduction type is grown prior to growing an epitaxial layer of the first conduction type onto the semiconductor wafer.

27. A method according to claim 24,

wherein

prior to growing an epitaxial layer of the first conduction type onto the semiconductor wafer or onto the pedestal epitaxial layer, an auxiliary layer is introduced epitaxially in regions of the trenches to be etched, which auxiliary layer enables an etching stop and preferably has Si_xGe_y where x>

y or Si_xGe_yC_z where x>

y and x>

z.

28. A method according to claim 27,

wherein

a composition of the auxiliary layer where 0.86≦

x≦

1, y≦

0.07 and z≦

0.07 is complied with.

29. A method according to claim 24,

wherein

prior to growing an epitaxial layer of the first conduction type onto the semiconductor wafer or onto the pedestal epitaxial layer, a patterned auxiliary layer is applied in regions of the trenches to be etched, which auxiliary layer enables an etching stop and preferably has a semiconductor oxide or semiconductor nitride, the structure of the auxiliary layer being applied in the regions of the trenches to be etched in a fine structure such that a lateral monocrystalline overgrowth of the fine structure is made possible.

30. A method according to claim 24

wherein

for the purpose of introducing the trench structure into the epitaxial layer of the first conduction type, an etching mask is applied photolithographically to the semiconductor wafer with strip-type patterns in the region of the drift path in the semiconductor component positions.

31. A method according to claim 24

wherein

an anisotropic and/or isotropic etching of the trench structure is effected for the purpose of introducing the trench structure.

32. A method according to claim 24,

wherein

an anisotropic reactive ion etching is carried out for the purpose of introducing the trench structure.

33. A method according to claim 24

wherein

a directional plasma etching is carried out for the purpose of introducing the trench structure.

34. A method according to claim 24,

wherein

a directional plasma etching with end point detection is carried out for the purpose of introducing the trench structure.

35. A method according to claim 24,

wherein

the photolithographic mask is removed, and the top side of the semiconductor wafer forms a first drift zone type with the fabricated mesas between the trenches.

36. A method according to claim 24

wherein

prior to applying the etching mask, a patterned end point control layer preferably made of a semiconductor oxide and/or a semiconductor nitride and/or an Si_xGe_yC_z layer where x>

y and x>

z, preferably with SiO_0.86 Ge_0.07 C_0.07, is applied, which covers the top sides of the first diffusion zone types.

37. A method according to claim 24,

wherein

after the introduction of the trench structure and prior to the doping of the trench walls the surfaces of the trench structure are chemically cleaned.

38. A method according to claim 24,

wherein

after the introduction of the trench structure and prior to the doping of the trench walls, the surface of the semiconductor wafer is oxidized and the oxide layer is subsequently etched away.

39. A method according to claim 24,

wherein

after the introduction of the trench structure and prior to the doping of the trench walls, the latter are smoothed by means of a hydrogen heat treatment step.

40. A method according to claim 24,

wherein

after the introduction of the trench structure and prior to the doping of the trench walls with a complementary conduction type, the mesas are doped from the gas phase for the purpose of adapting and increasing the concentration of the first conduction type in the mesas.

41. A method according to claim 24,

wherein

a relatively highly doped, complementarily conducting monocrystalline layer is grown epitaxially on the semiconductor wafer for the purpose of doping the trench structure walls to form charge compensation zones.

42. A method according to claim 24,

wherein

a relatively highly doped, complementarily conducting monocrystalline layer for doping the trench structure walls to form charge compensation zones is grown with a thickness d of between 100 nm≦

d≦

1000 nm, preferably 200 nm≦

d≦

600 nm.

43. A method according to claim 24,

wherein

for the purpose of doping the trench structure walls to form charge compensation zones, a doped glass layer is deposited on the areas of the trench structure, and the glass layer is removed after a diffusion step.

44. A method according to claim 24

wherein

a predoping from the gas phase with subsequent postdiffusion is effected for the purpose of doping the trench structure walls to form charge compensation zones.

45. A method according to claim 24,

wherein

an atomic layer deposition on the areas of the trench structure with subsequent indiffusion into the walls is effected for the purpose of doping the trench structure walls to form charge compensation zones.

46. A method according to claim 24,

wherein

after the doping of the trench structure walls to form charge compensation zones diffusion-inhibiting monocrystalline auxiliary layers are applied on the areas of the trench structure, which layers are provided in terms of construction and composition in accordance with claim 24.

47. A method according to claim 24,

wherein

after the doping of the trench structure walls to form charge compensation zones, a diffusion-inhibiting layer is deposited on the areas of the trench structure with a thickness of 10 nm≦

d≦

300 nm, preferably 50 nm≦

d≦

150 nm.

48. A method according to claim 24,

wherein

a dry etching method in accordance with claim 28 is used for the purpose of anisotropically etching free the bottom region of the trench structure and/or the top sides of the mesas of the first drift zone types.

49. A method according to claim 24,

wherein

prior to growing a medium-doped epitaxial layer of the first conduction type in the trench structure, the trench walls are etched in such a way that they have a bevel, so that the width at the top side of the semiconductor body is approximately equal to the width in the bottom region of the trench structure and the trench structure is in this case undercut approximately in barrel-shaped fashion.

50. A method according to claim 24,

wherein

prior to growing a medium-doped epitaxial layer of the first conduction type in the trench structure, the trench walls are etched in such a way that they have a bevel, so that the width of the trench structure at the top side of the semiconductor body becomes less than in the bottom region of the trench structure.

51. A method according to claim 24,

wherein

prior to growing a medium-doped epitaxial layer of the first conduction type in the trench structure, the trench walls are etched in such a way that they have a bevel, so that the width of the trench structure at the top side of the semiconductor body becomes greater than in the bottom region of the trench structure.

52. A method according to claim 24,

wherein

for the purpose of growing a medium-doped epitaxial layer of the first conduction type in the trench structure, as starting material for a second drift zone type, the epitaxial material is doped with carbon up to a concentration [C] of [C]≦

1×

10²⁰ cm<sup>−

3</sup>.

53. A method according to claim 24,

wherein

when growing a medium-doped epitaxial layer of the first conduction type in the trench structure, as starting material for a second drift zone type, the trench structure is not completely filled with epitaxial material and an oxide filling is provided as termination of the trench structure.

54. A method according to claim 24,

wherein

the trench structure is filled with intrinsically conducting polysilicon.

55. A method according to claim 24,

wherein

a chemical mechanical polishing method is used for the purpose of planarizing the top side of the semiconductor to form a semiconductor body with a planarized top side.

56. A method according to claim 24,

wherein

for the purpose of planarizing the top side of the semiconductor to form a semiconductor body with a planarized top side and rear side, firstly a leveling photoresist layer or a spin-on glass layer is applied to the uneven top side, the etching selectivity factor of which with respect to the semiconductor material of the drift cell types in conjunction with the etching or removal methods chosen is almost 1.

57. A method according to claim 24,

wherein

for the purpose of planarizing the top side of the semiconductor wafer as far as the grown drift zone types, the applied planarized photoresist layer or spin-on glass layer and the epitaxial material are etched back.

58. A method according to claim 24,

wherein

a proton implantation is carried out from the top side and/or from the rear side of the semiconductor wafer with annealing of the semiconductor wafer at temperatures T where 350°

C.≦

T≦

500°

C.

60. A method according to claim 58, wherein the method is used to produce n-doped regions in compensation structures in semiconductor components.

62. A method according to claim 60, wherein the semiconductor components are power semiconductor components.

59. A method comprising the step of using of a proton accelerator

for producing n-doped regions in semiconductor components.

61. A method according to claim 59, wherein the proton accelerator is a linear accelerator.

63. A method according to claim 59, wherein the semiconductor components are power semiconductor components.

65. A semiconductor component with charge compensation structure, comprising:

a drift path between two electrodes, wherein the drift path has drift zones of a first conduction type and charge compensation zones of a complementary conduction type, and wherein the drift zones comprise two alternately arranged, epitaxially grown drift zone types of the first conduction type,

a first drift zone type comprising monocrystalline semiconductor material on a monocrystalline substrate, and a second drift zone type comprising monocrystalline semiconductor material in a trench structure with complementarily doped walls, the complementarily doped walls forming the charge compensation zones.

66. A semiconductor component according to claim 65, wherein the semiconductor component is a power semiconductor component.