Formation of metal silicide layer over copper interconnect for reliability enhancement

• US 20070111522A1
• Filed: 11/12/2005
• Published: 05/17/2007
• Est. Priority Date: 11/12/2005
• Status: Active Grant

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Zhang, Hao, Lu, Wei, Gupta, Jyoti, Lim, Yeow, Hsia, Liang, Seet, Chim
• Granted Patent: US 7,790,617 B2
• Time in Patent Office: Days
• US Class Current: 438/682
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material

Abstract

A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form a copper interconnect in the interconnect opening. The copper interconnect is over polished to form a depression. We form metal silicide layer over the copper interconnect using a low temperature sputtering process. We can form a cap layer over the metal silicide layer.

Claims

1. A method of fabrication of a sputtered metal silicide layer over a copper interconnect;

comprising the steps of;

providing a dielectric layer over a semiconductor structure;

providing an interconnect opening in said dielectric layer;

providing a copper interconnect in said interconnect opening;

forming metal silicide layer over said copper interconnect using a sputter process.

2. The method of claim 1 which further includes planarizing said metal silicide layer to form a metal silicide cap.

3. The method of claim 1 wherein the metal silicide layer is formed using a sputter process at a temperature between 20 and 180 degrees C.

4. The method of claim 1 which further includes planarizing said metal silicide layer to form a metal silicide cap;

said metal silicide cap has a thickness between 100 and 200 angstroms;

said metal silicide layer is comprised of a material selected from the group consisting of;

WSi, CoSi, NiSi, and CuSi.

5. The method of claim 1 which further includes planarizing said metal silicide layer to form a metal silicide cap;

said metal silicide cap has a thickness between 100 and 200 angstroms;

said metal silicide layer is comprised of CuSi.

6. A method of fabrication of a sputtered metal silicide cap over a copper interconnect;

comprising the steps of;

forming a dielectric layer over a semiconductor structure;

forming an interconnect opening in said dielectric layer;

forming a copper layer at least filling said interconnect opening;

removing said copper layer over the dielectric layer to form a copper interconnect in said interconnect opening;

said copper interconnect has a top surface below the top surface of the surrounding dielectric layer;

forming metal silicide layer over said copper interconnect using a sputter process;

planarizing said metal silicide layer to form a metal silicide cap.

7. The method of claim 6 wherein said dielectric layer is comprised of TEOS or a low K material and has a thickness between 2000 and 6000 angstroms;

said interconnect opening has a dual damascene shape.

8. The method of claim 6 wherein the step of forming the copper layer comprises:

forming a pore sealant selectively over the dielectric layer in the interconnect opening;

the pore sealant is comprised of SiN, Parylene-N or Poly(p-xylyene);

forming a barrier layer over the dielectric layer;

said barrier layer comprised of a material from the group consisting of TiN or TiSiN, Ta, and TaN and has a thickness between 150 and 300 angstroms;

forming a Cu seed layer over said barrier layer;

the Cu seed layer is a PVD Cu layer with a thickness between 300 and 600 angstroms;

forming said copper layer by an electroplating process over said seed layer.

9. The method of claim 6 wherein the step of removing the copper layer comprises planarizing said copper layer to remove said copper layer over the top surface of said dielectric layer outside of the interconnect opening and remove a barrier metal layer outside of the interconnect opening, and planarizing the copper interconnect to a level between 100 and 200 angstroms below the top surface of said dielectric layer outside of the interconnect opening.

10. The method of claim 6 wherein the top surface of said copper interconnect is below the top surface of said dielectric layer a distance between about 100 and 200 angstroms.

11. The method of claim 6 wherein the metal silicide layer is formed using a sputter process at a temperature between 20 and 180 degrees C.

12. The method of claim 6 wherein said metal silicide layer is comprised of a material selected from the group consisting of:

WSi, CoSi, NiSi, and CuSi.

13. The method of claim 6 wherein said metal silicide layer has a thickness between 500 and 800 angstroms.

14. The method of claim 6 wherein the metal silicide layer is form using a sputtering process comprises:

a target comprised substantially of metal and Si a Si/Metal atomic ratio of between 2.7 and 2.9, a DC power for sputtering is between 1000 to 3000 W;

Ar gas as sputtering gas;

a pressure less than 10 mtorr.;

a temperature between 20 and 180 degrees C.

15. The method of claim 6 wherein said metal silicide cap has a thickness between 100 and 200 angstroms.

16. The method of claim 6 wherein the metal silicide layer is formed using a sputter process at a temperature between 20 and 180 degree C.;

said metal silicide layer is comprised substantially of copper silicide.

17. A method of fabrication of a sputtered metal silicide layer over a copper interconnect;

comprising the steps of;

forming a conductive layer over a semiconductor structure;

forming a capping layer over said conductive layer;

forming a dielectric layer over said capping layer and said conductive layer;

forming an interconnect opening in said dielectric layer;

said interconnect opening has a dual damascene shape;

forming a copper layer at least filling said interconnect opening;

(1) said copper layer is formed by an electroplating or electroless process;

planarizing said copper layer to form a copper interconnect in said interconnect opening;

said copper interconnect has a top surface between about 100 and 300 angstroms below the top surface of the surrounding dielectric layer;

forming a metal silicide layer over said copper interconnect using a sputter process;

(1) the metal silicide layer is formed using a sputter process at a temperature between 20 and 180 degree C.;

(2) said metal silicide layer is comprised of a material selected from the group consisting of;

WSi, CoSi, NiSi, and CuSi;

planarizing said metal silicide layer to form a metal silicide cap.

18. The method of claim 17 which further includes forming a cap layer over the metal silicide cap and dielectric layer;

the cap layer is comprised of a material selected from the group consisting of;

dielectric materials, SiN, SiC(O), SiC(N).

19. The method of claim 17 wherein The step of forming the copper layer comprises:

forming a pore sealant selectively over the dielectric layer in the interconnect opening;

the pore sealant is comprised of SiN, Parylene-N or Poly(p-xylyene);

forming a barrier layer over the dielectric layer;

said barrier layer comprised of a material from the group consisting of TiN, TiSiN, Ta, or TaN; and

has a thickness between 150 and 200 angstroms;

forming a Cu seed layer over said barrier layer;

the Cu seed layer is a PVD Cu layer with a thickness between 50 and 500 angstroms;

forming said copper layer by an electroplating process over said Cu seed layer.

20. The method of claim 17 wherein the metal silicide layer is formed using a sputtering process comprising:

a target comprised substantially of metal and Si with a Si/W atomic ratio of between 2.7 and 2.9;

a DC power for sputtering is between 1000 to 3000 W;

Ar gas as sputtering gas;

a pressure less than 10 mtorr.;

a temperature between 20 and 180 degrees C.

21. The method of claim 17 wherein the metal silicide layer comprised substantially of copper silicide and is formed using a sputtering process comprising:

a target comprised substantially of copper and Si with a Si/Cu atomic ratio of between 2.7 and 2.9;

a DC power for sputtering is between 1000 to 3000 W;

Ar gas as sputtering gas;

a pressure less than 10 mtorr.;

a temperature between 20 and 180 degrees C.

22. The method of claim 17 wherein said metal silicide cap has a thickness between 100 and 200 angstroms.