Generation of metal holes by via mutation

• US 20070118828A1
• Filed: 01/16/2007
• Published: 05/24/2007
• Est. Priority Date: 11/06/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG), International Business Machines Corporation, United Microelectronics Corporation
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG), International Business Machines Corporation, United Microelectronics Corporation
• Inventors: Leung, Pak, Wong, Robert, Demm, Ernst, Hirsch, Alexander
• Granted Patent: US 7,875,544 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Claims

1. A method of producing a semiconductor interconnect architecture, the method comprising:

providing a first metal layer;

providing a second metal layer;

providing a plurality of conductive vias interconnecting said first and second metal layers; and

said first-mentioned providing step including providing a plurality of holes in the first metal layer at respectively corresponding predetermined positions relative to respective ones of said plurality of vias.

2. The method of claim 1, wherein some of said plurality of vias have a first cross-sectional area and others of said plurality of vias have a second cross-sectional area that differs from said first cross-sectional area.

3. The method of claim 2, wherein some of said holes have a cross-sectional area that is greater than a cross-sectional area of some of said vias.

4. The method of claim 1, wherein some of said holes have a cross-sectional area that is greater than a cross-sectional area of some of said vias.

5. The method of claim 1, wherein said holes are approximately equidistantly offset from respective points in the first metal layer that are in a relatively overlying relationship with the corresponding ones of said plurality of vias.

6. A semiconductor interconnect architecture, the architecture comprising:

a first metal layer;

a second metal layer;

a plurality of conductive vias interconnecting said first and second metal layers; and

said first metal layer having provided therein a plurality of holes at respectively corresponding predetermined positions relative to respective ones of said plurality of vias.

7. The semiconductor interconnect architecture of claim 6, wherein some of said plurality of vias have a first cross-sectional area and others of said plurality of vias have a second cross-sectional area that differs from said first cross-sectional area.

8. The semiconductor interconnect architecture of claim 7, wherein some of said holes have a cross-sectional area that is greater than a cross-sectional area of some of said vias.

9. The semiconductor interconnect architecture of claim 6, wherein some of said holes have a cross-sectional area that is greater than a cross-sectional area of some of said vias.

10. The semiconductor interconnect architecture of claim 6, wherein said holes are approximately equidistantly offset from respective points in the first metal layer that are in a relatively overlying relationship with the corresponding ones of said plurality of vias.