Multi-threshold CMOS latch circuit
First Claim
1. A multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit, comprising:
- a data inverting circuit for inverting and outputting input data under the control of a sleep control signal;
a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal;
a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and
a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode, wherein the feedback circuit comprises;
a second inverter for inverting and outputting the signal output from the signal control circuit;
a third p-channel metal oxide semiconductor (PMOS) transistor having a source for receiving the signal output from the signal control circuit, a gate for receiving the signal output from the second inverter, and a drain connected to an output; and
a third n-channel metal oxide semiconductor (NMOS) transistor having a drain connected to a logic gate of the signal control circuit, a gate for receiving the signal output from the second inverter, and a source connected to ground.
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Accused Products
Abstract
Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.
19 Citations
13 Claims
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1. A multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit, comprising:
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a data inverting circuit for inverting and outputting input data under the control of a sleep control signal;
a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal;
a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and
a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode, wherein the feedback circuit comprises;
a second inverter for inverting and outputting the signal output from the signal control circuit;
a third p-channel metal oxide semiconductor (PMOS) transistor having a source for receiving the signal output from the signal control circuit, a gate for receiving the signal output from the second inverter, and a drain connected to an output; and
a third n-channel metal oxide semiconductor (NMOS) transistor having a drain connected to a logic gate of the signal control circuit, a gate for receiving the signal output from the second inverter, and a source connected to ground. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification