Adaptable Detection Threshold for RFID Tags and Chips

• US 20070126584A1
• Filed: 02/02/2007
• Published: 06/07/2007
• Est. Priority Date: 04/13/2004
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impimj Incorporated
• Inventors: Sundstrom, Kurt, Hyde, John
• Granted Patent: US 7,917,088 B2
• Time in Patent Office: Days
• US Class Current: 340/572.400
• CPC Class Codes: H04B 5/0062 in RFID [Radio Frequency Identification] Systems
• CPC Class Codes: H04B 5/02 using transceiver
• CPC Class Codes: H04B 5/48 Transceivers
• CPC Class Codes: H04B 5/77 for interrogation

Abstract

RFID tags, tag circuits, and methods are provided that reduce at least in part the distortion to received wireless signals, which is caused by interference in the environment. Two or more thresholds are used to digitize the received signal implemented by two or more demodulators. Multiple low pass and digital filters may be implemented with the demodulators, allowing removal of narrow pulses caused by the interference and reduction of beat tone amplitude.

Claims

1. A dual threshold circuit of a Radio Frequency Identification (RFID) tag, comprising:

a first circuit operable to derive an unfiltered input from a wireless signal received by the tag, the wireless signal including distortion due to interference;

a second circuit operable to generate two digital outputs from the unfiltered input using two distinct decision thresholds; and

a selection circuit operable to generate a filtered output by selecting one of the digital outputs.

2. The dual threshold circuit of claim 1, further comprising:

two digital filters, each for filtering a respective one of the two digital outputs, an artifact feature deriving from the distortion thereby being removed from at least one of the digital outputs.

3. The dual threshold circuit of claim 2, in which

at least one of the digital filters is a narrow pulse digital filter.

4. The dual threshold circuit of claim 2, in which

each digital filter includes at least one filter having a distinct narrow pulse digital filter for each digital output.

5. The dual threshold circuit of claim 2, in which

one of the filters is set to detect all data rates;

and

at least one of the remaining filters is set to detect a subset of the data rates.

6. The dual threshold circuit of claim 5, in which

the filter set to detect all data rates includes an aperture set to a minimum width.

7. The dual threshold circuit of claim 1, in which

one of the unfiltered input and filtered output includes a number.

8. The dual threshold circuit of claim 1, in which

one of the unfiltered input and filtered output includes a signal.

9. The dual threshold circuit of claim 1, in which

the filtered output is generated based on a performance criterion resulting in an artifact feature deriving from the distortion being removed.

10. The dual threshold circuit of claim 1, in which

the first circuit includes an envelope detector.

11. The dual threshold circuit of claim 1, in which

the selection circuit includes a multiplexer.

12. The dual threshold circuit of claim 1, in which

the second circuit includes two distinct slicers for generating the digital outputs with each slicer using a distinct decision threshold.

13. The dual threshold circuit of claim 12, in which

the second circuit includes at least one additional slicer using a further distinct decision threshold.

14. The dual threshold circuit of claim 12, in which

at least a portion of the circuitry for the slicers is common.

15. The dual threshold circuit of claim 12, in which

the slicers receive power until a performance criterion is met that is associated with detecting one of a frame synch and a preamble;

once the performance criterion is met, one of the slicers is selected to decode the input; and

the other slicer no longer receives power.

16. The dual threshold circuit of claim 12, in which

the selection circuit is configured to select one of the slicers for generating the ultimately selected digital output.

17. The dual threshold circuit of claim 16, in which

the selection circuit is configured to select based on:

detecting a falling edge of a symbol following an RTcal signal; and

if a higher threshold slicer has detected the falling edge, using the higher threshold slicer to generate the digital output,

else if a lower threshold slicer has detected the falling edge, using the lower threshold slicer to generate the digital output.

18. The dual threshold circuit of claim 1, in which

the selection circuit includes

a multiplexer for selecting one of the digital outputs, and

a digital decision circuit for configuring the multiplexer.

19. The dual threshold circuit of claim 1, in which

the second circuit includes a demodulator, and

the selection circuit is further configured to:

determine a data rate of the unfiltered input; and

adjust a clock frequency of the demodulator based on the determined data rate.

20. The dual threshold circuit of claim 19, in which

the demodulator clock frequency is adjusted by reducing the clock frequency if the data rate is below a predefined value.

21. The dual threshold circuit of claim 19, in which

the demodulator clock frequency is adjusted based on which demodulator circuit is selected to generate the ultimately selected digital output.

22. The dual threshold circuit of claim 1, in which

the second circuit includes an Analog-Digital-Converter (ADC).

23. The dual threshold circuit of claim 1, further comprising:

a low pass filter circuit for filtering the unfiltered input before generating the digital outputs.

24. The dual threshold circuit of claim 23, in which

the low pass filter circuit includes a distinct low pass filter for each of the digital signals.

25. The dual threshold circuit of claim 23, in which

each low pass filter is configured to have a distinct bandwidth.

26. A method for a circuit of an RFID tag, comprising:

deriving an unfiltered input from a wireless signal received by the tag, the wireless signal including distortion due to interference;

generating two digital outputs from the unfiltered input using two distinct decision thresholds;

generating a filtered output by selecting one of the digital outputs; and

performing an operation responsive to the filtered output.

27. The method of claim 26, in which

one of the unfiltered input and filtered output includes a number.

28. The method of claim 26, in which

one of the unfiltered input and filtered output includes a signal.

29. The method of claim 26, in which

one of the digital outputs is selected based on a detection criterion.

30. The method of claim 29, in which

the detection criterion includes detecting at least one from a set of:

a frame synch, a preamble, and a command.

31. The method of claim 26, in which

both digital outputs are received in a multiplexer, and

the filtered output is an output from the multiplexer.

32. The method of claim 26, further comprising:

generating an additional digital output using an additional decision threshold; and

filtering the additional digital output using a digital filter.

33. The method of claim 26, further comprising:

filtering each digital output employing respective digital filters, an artifact feature deriving from the distortion thereby being removed from at least one of the digital outputs.

34. The method of claim 33, in which

at least one of the digital filters is a narrow pulse digital filter.

35. The method of claim 34, in which

the narrow pulse digital filter comprises a plurality of filters with a distinct narrow pulse digital filter for each digital output.

36. The method of claim 33, further comprising:

setting one of the filters to detect all data rates; and

setting at least one of the remaining filters to detect a subset of the data rates.

37. The method of claim 36, in which

setting one of the plurality of filters to detect all data rates includes setting an aperture of the filter to a minimum width.

38. The method of claim 26, in which

two demodulator circuits are used, each to generate a respective one of the digital outputs.

39. The method of claim 38, further comprising:

applying power to the demodulator circuits until a performance criterion is met, the performance criterion signifying that a frame synch has been detected;

then selecting one of the demodulator circuits to generate the digital output; and

discontinuing applying power to the other demodulator circuit.

40. The method of claim 39, in which

selecting the demodulator circuit is performed by:

detecting a falling edge of a symbol following an RTcal signal; and

if a higher threshold demodulator circuit has detected the falling edge, using the higher threshold demodulator circuit to generate the digital output,

else if a lower threshold demodulator circuit has detected the falling edge, using the lower threshold slicer to generate the digital output.

41. The method of claim 39, further comprising:

determining a data rate of the input; and

adjusting a clock frequency of at least one of the demodulator circuits based on the determined data rate.

42. The method of claim 41, in which

adjusting the demodulator circuit clock frequency includes reducing the clock frequency if the data rate is below a predefined value.

43. The method of claim 41, in which

the demodulator circuit clock frequency is adjusted based on which demodulator circuit is selected to generate the digital output.

44. The method of claim 26, further comprising:

low pass filtering the unfiltered input before generating the digital outputs from it.

45. The method of claim 44, in which

low pass filtering the unfiltered input includes employing a distinct low pass filter for each of the digital outputs, the low pass filters having different bandwidths.

46. A method comprising:

providing schematic-type inputs for the purpose of preparing a layout that embodies the inputs, in which, if the layout is incorporated in a tapeout file that is used by mask making machinery as instructions for processing a semiconductor wafer, an integrated circuit for use in an RFID tag having an antenna will result on the wafer according to the inputs, comprising;

a first and a second antenna pads that can be coupled to the antenna; and

a component that includes;

a first circuit operable to derive an unfiltered input from a wireless signal received by the tag, the wireless signal including distortion due to interference;

a second circuit for generating two digital outputs from the unfiltered input using two distinct decision thresholds; and

a selection circuit for generating a filtered output by selecting one of the digital outputs.

47. The method of claim 46, in which

the component further includes:

two digital filters, each for filtering a respective one of the two digital outputs, an artifact feature deriving from the distortion thereby being removed from at least one of the digital outputs.

48. The method of claim 47, in which

at least one of the digital filters is a narrow pulse digital filter.

49. The method of claim 48, in which

each digital filter includes at least one filter having a distinct narrow pulse digital filter for each digital output.

50. The method of claim 47, in which

one of the filters is set to detect all data rates;

and

at least one of the remaining filters is set to detect a subset of the data rates.

51. The method of claim 50, in which

the filter set to detect all data rates includes an aperture set to a minimum width.

52. The method of claim 46, in which

one of the unfiltered input and filtered output includes a number.

53. The method of claim 46, in which

one of the unfiltered input and filtered output includes a signal.

54. The method of claim 46, in which

the filtered output is generated based on a performance criterion resulting in an artifact feature deriving from the distortion being removed.

55. The method of claim 46, in which

the first circuit includes an envelope detector.

56. The method of claim 46, in which

the selection circuit includes a multiplexer.

57. The method of claim 46, in which

the second circuit includes two distinct slicers for generating the digital outputs with each slicer using a distinct decision threshold.

58. The method of claim 46, in which

the selection circuit includes a multiplexer for selecting one of the digital outputs;

and

a digital decision circuit for configuring the multiplexer based on the performance criterion.

59. The method of claim 46, in which

the second circuit includes an Analog-Digital-Converter (ADC).

60. The method of claim 46, in which

the component further includes:

a low pass filter circuit for filtering the unfiltered input before generating the digital outputs.

61. An article comprising a machine-readable memory containing thereon instructions which, if executed by mask making machinery as instructions for processing a semiconductor wafer, an integrated circuit for use in an RFID tag having an antenna will result on the wafer, comprising:

a first and a second antenna pads that can be coupled to the antenna; and

a component that includes;

a first circuit operable to derive an unfiltered input from a wireless signal received by the tag, the wireless signal including distortion due to interference;

a second circuit for generating two digital outputs from the unfiltered input using two distinct decision thresholds; and

a selection circuit for generating a filtered output by selecting one of the digital outputs.

62. The article of claim 61, in which

the component further includes:

two digital filters, each for filtering a respective one of the two digital outputs, an artifact feature deriving from the distortion thereby being removed from at least one of the digital outputs.

63. The article of claim 62, in which

at least one of the digital filters is a narrow pulse digital filter.

64. The article of claim 62, in which

each digital filter includes at least one filter having a distinct narrow pulse digital filter for each digital output

65. The article of claim 61, in which

the first circuit is an envelope detector.

66. The article of claim 61, in which

the selection circuit includes a multiplexer.

67. The article of claim 61, in which

the second circuit includes two distinct slicers for generating the digital outputs with each slicer using a distinct decision threshold.

68. The article of claim 61, in which

the selection circuit includes a multiplexer for selecting one of the digital outputs;

and

a digital decision circuit for configuring the multiplexer based on the performance criterion.

69. The article of claim 61, in which

the second circuit includes an Analog-Digital-Converter (ADC).

70. The article of claim 61, in which

the component further includes:

a low pass filter circuit for filtering the unfiltered input before generating the digital outputs.