Nonvolatile semiconductor memory

• US 20070127295A1
• Filed: 01/25/2007
• Published: 06/07/2007
• Est. Priority Date: 07/06/1992
• Status: Active Grant

• Current Assignee: Emergence Memory Solutions LLC
• Original Assignee: Solid State Storage Solutions, Inc.
• Inventors: Kume, Hitoshi, Tanaka, Toshihiro, Kato, Masataka, Sasaki, Toshio, Kimura, Katsutaka, Adachi, Tetsuo
• Granted Patent: US 7,366,016 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Claims

1. A data storing apparatus comprising:

a controller; and

a plurality of nonvolatile memories,

wherein each of the nonvolatile memories comprises an address buffer for holding address information supplied from the controller and a plurality of nonvolatile memory cells, and is capable of receiving data from the controller, in response to pulses supplied from the controller, and after then starts to program data into ones of nonvolatile memory cells thereof selected by the address information, and

wherein the controller (i) transfers data to a first nonvolatile memory of the plurality of nonvolatile memories in response to supplying the pulses to the first nonvolatile memory, (ii) stops supplying the pulses to the first nonvolatile memory with ending of the data outputting, and after then (iii) is capable of starting the transfer of data to a second nonvolatile memory of the plurality of nonvolatile memories in response to supplying the pulses to the second nonvolatile memory.

2. A data storing apparatus according to claim 1,

wherein the controller supplies address information to a corresponding nonvolatile memory before supplying data.

3. A data storing apparatus according to claim 2,

wherein the controller is supplied with first address information from outside of the data storing apparatus, and comprises a decoder means for selecting one of the nonvolatile memories in accordance with the first address information.

4. A data storing apparatus according to claim 3,

wherein each of the nonvolatile memories further comprises an address decoder and a plurality of word lines, each of the word lines is coupled with corresponding memory cells, and each of the nonvolatile memories selects one of the word lines in accordance with the address information supplied from the controller and decoded by the address decoder thereof.

5. A data storing apparatus according to claim 4,

wherein each of the nonvolatile memories further comprises a data buffer for holding data supplied from the controller, temporarily.

6. A data storing apparatus according to claim 5,

wherein each of the nonvolatile memories is capable of receiving the data, the amount of which is matched with the amount of data to be programmed to ones of the nonvolatile memory cells coupled with one word line, from the controller.

7. A data storing apparatus comprising:

a control circuit; and

a plurality of nonvolatile memories each of which comprises an address buffer and a nonvolatile memory array,

wherein each of the nonvolatile memories receives from the control circuit address information for holding in the address buffer thereof and data for programming into each nonvolatile memory array, and

wherein the control circuit supplies first address information and first data to a first nonvolatile memory of the plurality of nonvolatile memories, after then is capable of supplying second address information and second data to a second nonvolatile memory of the plurality of nonvolatile memories during programming of the first data in the first nonvolatile memory.

8. A data storing apparatus according to claim 7,

wherein an address from outside of the data storing apparatus is received, and

wherein the control circuit uses the address received from outside for selecting one of the nonvolatile memories to be supplied with the address information and data, and generates the address information to supply to the selected one of the nonvolatile memories.

9. A data storing apparatus according to claim 8, being coupled to a host system via a predetermined bus standard.

10. A data storing apparatus according to claim 9,

wherein the predetermined bus standard is the Intelligent Device Electronics (IDE) standard.

11. A data storing apparatus comprising:

a controller; and

at least a first nonvolatile memory and a second nonvolatile memory, each of which comprises an address buffer for holding address information supplied from the controller and a plurality of nonvolatile memory cells,

wherein each of the nonvolatile memories is coupled to receive data from the controller, in response to pulses supplied from the controller, and after then starts to program data into ones of nonvolatile memory cells thereof selected by the address information, and

wherein the controller (i) transfers data to the first nonvolatile memory in response to supplying the pulses to the first nonvolatile memory, (ii) stops supplying the pulses to the first nonvolatile memory with ending of data outputting, and after then (iii) is enabled for starting the transfer of data to the second nonvolatile memory in response to supplying the pulses to the second nonvolatile memory.

12. A data storing apparatus according to claim 11,

wherein the controller supplies address information to a corresponding nonvolatile memory before supplying data.

13. A data storing apparatus according to claim 12,

wherein the controller is supplied with first address information from outside of the data storing apparatus, and comprises a decoder means for selecting one of the nonvolatile memories in accordance with the first address information.

14. A data storing apparatus according to claim 13,

wherein each of the nonvolatile memories further comprises an address decoder and a plurality of word lines, each of the word lines is coupled with corresponding memory cells, and each of the nonvolatile memories selects one of the word lines in accordance with the address information supplied from the controller and decoded by the address decoder thereof.

15. A data storing apparatus according to claim 14,

wherein each of the nonvolatile memories further comprises a data buffer for holding data supplied from the controller, temporarily.

16. A data storing apparatus according to claim 15,

wherein each of the nonvolatile memories is configured to receive the data, the amount of which is matched with the amount of data to be programmed to ones of the nonvolatile memory cells coupled with one word line, from the controller.

17. A data storing apparatus comprising:

a control circuit; and

at least a first nonvolatile memory and a second nonvolatile memory each of which comprises an address buffer and a nonvolatile memory array,

wherein each of the first and second nonvolatile memories receives from the control circuit address information for holding in the address buffer thereof and data for programming into each nonvolatile memory array, and

wherein the control circuit supplies first address information and first data to the first nonvolatile memory, after then is enabled for supplying second address information and second data to the second nonvolatile memory during programming of the first data in the first nonvolatile memory.

18. A data storing apparatus according to claim 17,

wherein an address from outside of the data storing apparatus is received, and

wherein the control circuit uses the address received for selecting one of the first and second nonvolatile memories to supply the address information and data, and generates the address information to supply to the selected one of the nonvolatile memories.

19. A data storing apparatus according to claim 18, being coupled to a host system via a predetermined bus standard.

20. A data storing apparatus according to claim 19, wherein the predetermined bus standard is the Intelligent Device Electronics (IDE) standard.

21. A memory system comprising:

a first nonvolatile semiconductor memory and a second nonvolatile semiconductor memory each including a memory cell array containing a plurality of nonvolatile memory cells which are disposed at a surface region of a semiconductor substrate, each of the plurality of nonvolatile memory cells being adapted for setting one of a program state and an erase state;

a first data bus to which program data is provided from outside of the memory system;

a first control bus to which a first program signal is provided from outside of the memory system;

an interface part coupled to both the first control bus and the first data bus;

a second data bus coupled to both the interface part and the first and second nonvolatile semiconductor memories, the second data bus being enabled to transmit transmission data, corresponding to the program data, from the interface part; and

a second control bus coupled to the first and second nonvolatile semiconductor memories and to the interface part, the second control bus being enabled to transmit a second program signal corresponding to the first program signal,

wherein the second program signal controls the first and second nonvolatile semiconductor memories in which the setting of the program state to a corresponding memory cell is performed by a program operation of programming data corresponding to the transmission data, and

wherein the program operation of the first nonvolatile semiconductor memory is overlapped with at least one of

(i) a receive operation of the second nonvolatile semiconductor memory, including receiving of the transmission data from the second data bus, and

(ii) the program operation of the second nonvolatile semiconductor memory.

22. The memory system according to claim 21,

wherein each of the first and second nonvolatile semiconductor memories contains a means for the temporary holding of the transmission data received from the second data bus.

23. A memory system comprising:

a first data bus to which a first program data is provided from outside of the memory system;

a first control bus to which a program control signal is provided from outside of the memory system;

processor means coupled to the first control bus and to the first data bus;

a first nonvolatile semiconductor memory and a second nonvolatile semiconductor memory each including a memory cell array containing a plurality of nonvolatile memory cells,

wherein each of the nonvolatile memory cells has a source region and a drain region disposed in a surface region of a semiconductor substrate in a mutually spaced-apart relationship, a gate insulating film extended on at least a channel region, a floating gate formed on the gate insulation film, an intermediate insulating film formed on the floating gate, and a control gate formed on the intermediate insulating film, and is capable of setting one of a program state and an erase state by transferring an electric charge according to a tunnel mechanism between the surface region and the floating gate, and

wherein each of the first and second nonvolatile semiconductor memories includes a data holding part for holding second program data based on program data;

a second data bus coupled to both the processor means and the first and second nonvolatile semiconductor memories, the second data bus being coupled to transmit the program data, based on the first program data from the processor means, to the first and second nonvolatile memories; and

a second control bus coupled to the first and second nonvolatile semiconductor memories and to the processor means, the second control bus being for transmitting a control signal based on the program control signal.

24. The memory system according to claim 23,

wherein the memory system is adapted for operating a first program operation of a data, based on the second program data, to one or more memory cells of the first nonvolatile semiconductor memory in parallel to at least one of

(i) a transmit operation transmitting program data to the second nonvolatile semiconductor memory via the second data bus, and

(ii) a second program operation of second program data held in the holding part of the second nonvolatile semiconductor memory.

25. The memory system according to claim 24,

wherein the processor means includes a transmission part for receiving the first program data and transmitting corresponding program data to the second data bus.

26. A memory system comprising:

a first nonvolatile semiconductor memory and a second nonvolatile semiconductor memory each including a memory cell array containing a plurality of nonvolatile memory cells which are disposed at a surface region of a semiconductor substrate, each of the plurality of nonvolatile memory cells being adapted for setting one of a program state and an erase state by transferring an electric charge according to a tunnel mechanism between the surface region and a floating gate thereof, the first and second nonvolatile semiconductor memories being capable of overlapping a first program operation period of a first program data to program one or more memory cells of one of the first and second nonvolatile semiconductor memories and at least one of

(i) an input operation period of the other of the first and second nonvolatile semiconductor memories, associated with a second program data, and

(ii) a second program operation period of the second program data to program one or more memory cells of the other of the first and second nonvolatile semiconductor memories;

a first data bus to which is provided program data from outside of the memory system;

a first control bus to which a first signal for programming is provided from outside of the memory system;

an interface part coupled to both the first control bus and the first data bus;

a second data bus coupled to both the interface part and the first and the second nonvolatile semiconductor memories, the second data bus being enabled to transmit the first program data or the second program data, selectively, corresponding to program data from the interface part; and

a second control bus coupled to the first and second nonvolatile semiconductor memories and to the interface part, the second control bus being enabled to transmit a second signal for programming corresponding to the first signal.

27. The memory system according to claim 26,

wherein the interface part includes a transmission circuit for receiving the program data and transmitting the first and the second program data to the second data bus.

28. The memory system according to claim 27,

wherein each of the first and second nonvolatile semiconductor memories contains a means for the temporary holding of the data received from the second data bus.