Load compensation circuit and pre-power amplifier constructed therefrom

• US 20070129029A1
• Filed: 12/01/2005
• Published: 06/07/2007
• Est. Priority Date: 12/01/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Litmanen, Petteri
• Granted Patent: US 7,586,376 B2
• Time in Patent Office: Days
• US Class Current: 455/126
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2200/366 Multiple MOSFETs are coupled in parallel
• CPC Class Codes: H03F 2203/21145 Output signals are combined by switching a plurality of paralleled power amplifiers to a common output
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H04B 1/0458 Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages matching circuits in general H03H

Abstract

A novel and useful load compensation circuit and associated pre-power amplifier constructed therefrom. The load compensation circuit functions to maintain a nearly constant output impedance of the pre-power amplifier by use of a switch matrix comprising a plurality of transistors. The switch matrix is placed in parallel with the output of the pre-power amplifier (PPA). Transistors are turned on or off within the load compensation switch matrix so as to maintain a nearly constant output impedance of the PPA throughout the entire modulation range. At maximum PPA output power, all transistors in the load compensation switch matrix are turned off thereby minimizing the extra output loading and reducing the overall power output. As output power decreases, additional numbers of transistors in the load compensation switch matrix are turned on so as to maintain a constant output impedance of the PPA.

Claims

1. A load compensation circuit, comprising:

a switch matrix; and

load control means coupled to said switch matrix, said load control means operative to vary the amount of load coupled to the output of a circuit in accordance with a load control signal such that the output impedance of said circuit is maintained at a substantially constant value.

2. The circuit according to claim 1, wherein said circuit comprises a pre-power amplifier and said load control signal is determined in accordance with the most significant bit (MSB) setting of said pre-power amplifier.

3. The circuit according to claim 1, wherein said circuit comprises a pre-power amplifier and said load control means comprises a look up table (LUT) incorporating control data for all possible values of the most significant bit (MSB) setting of said pre-power amplifier.

4. The circuit according to claim 1, wherein said level value is approximately 50 ohms.

5. The circuit according to claim 1, wherein said switch matrix comprises a plurality of transistors connected between said output and ground, wherein a portion of said transistors are turned on in accordance with said load control signal.

6. The circuit according to claim 1, wherein said load control means comprises means for varying the load coupled to said output in accordance with predetermined values selected based on the number of devices active in said circuit at any point in time.

7. The circuit according to claim 1, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

8. The circuit according to claim 1, adapted to be implemented in a Field Programmable Gate Array (FPGA).

9. A pre-power amplifier, comprising:

a load coupled to a power source;

a switch array comprising a plurality of switches, said switch array for generating a current proportional to the number of switches active therein; and

a load compensation circuit coupled to said switch array, said load compensation circuit operative to vary the load coupled to the output of said pre-power amplifier in accordance with a load control signal such that the output impedance of said pre-power amplifier is maintained at a substantially constant value.

10. The amplifier according to claim 9, wherein said switch array comprises at least one transistor matrix.

11. The amplifier according to claim 9, wherein said switch array comprises a most significant bit (MSB) transistor matrix.

12. The amplifier according to claim 9, wherein said switch array comprises a least significant bit (LSB) transistor matrix.

13. The amplifier according to claim 9, wherein said switch array comprises a sigma-delta dithering (SD) transistor matrix.

14. The amplifier according to claim 9, wherein said load control signal is determined in accordance with the most significant bit (MSB) setting of said switch array.

15. The amplifier according to claim 9, wherein said load control means comprises a look up table (LUT) incorporating control data for all possible values of the most significant bit (MSB) setting of said switch array.

16. The amplifier according to claim 9, wherein said level value is approximately 50 ohms.

17. The amplifier according to claim 9, wherein said load compensation circuit comprises a switch matrix comprising a plurality of transistors connected between said output and ground, wherein a portion of said transistors are turned on in accordance with said load control signal, adding impedance to said output.

18. The amplifier according to claim 9, wherein said load compensation circuit comprises means for varying the load coupled to said output in accordance with predetermined values selected based on the number of devices active in said switch array at any point in time.

19. The amplifier according to claim 9, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

20. The amplifier according to claim 9, adapted to be implemented in a Field Programmable Gate Array (FPGA).

21. A pre-power amplifier, comprising:

a load coupled to a power source;

a switch array comprising a plurality of switches, said switch array for generating a current proportional to the number of switches active therein;

a load compensation circuit coupled to said switch array, comprising a switch matrix; and

load control means coupled to said switch matrix, said load control means operative to vary the amount of load coupled to the output of said pre-power amplifier in accordance with a load control signal such that the output impedance of said circuit is maintained at a substantially constant value.

22. The amplifier according to claim 21, wherein said switch array comprises at least one transistor matrix.

23. The amplifier according to claim 21, wherein said switch array comprises a most significant bit (MSB) transistor matrix.

24. The amplifier according to claim 21, wherein said switch array comprises a least significant bit (LSB) transistor matrix.

25. The amplifier according to claim 21, wherein said switch array comprises a sigma-delta dithering (SD) transistor matrix.

26. The amplifier according to claim 21, wherein said load control signal is determined in accordance with the most significant bit (MSB) setting of said switch array.

27. The amplifier according to claim 21, wherein said load control means comprises a look up table (LUT) incorporating control data for all possible values of the most significant bit (MSB) setting of said switch array.

28. The amplifier according to claim 21, wherein said level value is approximately 50 ohms.

29. The amplifier according to claim 21, wherein said switch matrix comprises a plurality of transistors connected between said output and ground, wherein a portion of said transistors are turned on in accordance with said load control signal, adding impedance to said output.

30. The amplifier according to claim 21, wherein said load compensation circuit comprises means for varying the load coupled to said output in accordance with predetermined values selected based on the number of devices active in said switch array.

31. The amplifier according to claim 21, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

32. The amplifier according to claim 21, adapted to be implemented in a Field Programmable Gate Array (FPGA).

33. A pre-power amplifier, comprising:

a load coupled to a power source;

a switch array comprising a plurality of switches, said switch array for generating a current proportional to the number of switches active therein; and

load compensation means coupled to said switch array for varying the amount of load coupled to the output of said pre-power amplifier in accordance with a load control signal such that the output impedance of said circuit is maintained at a substantially constant value.

34. The amplifier according to claim 33, wherein said switch array comprises at least one transistor matrix.

35. The amplifier according to claim 33, wherein said switch array comprises a most significant bit (MSB) transistor matrix.

36. The amplifier according to claim 33, wherein said switch array comprises a least significant bit (LSB) transistor matrix.

37. The amplifier according to claim 33, wherein said switch array comprises a sigma-delta dithering (SD) transistor matrix.

38. The amplifier according to claim 33, wherein said load control signal is determined in accordance with the most significant bit (MSB) setting of said switch array.

39. The amplifier according to claim 33, wherein said load control means comprises a look up table (LUT) incorporating control data for all possible values of the most significant bit (MSB) setting of said switch array.

40. The amplifier according to claim 33, wherein said level value is approximately 50 ohms.

41. The amplifier according to claim 33, wherein said switch matrix comprises a plurality of transistors connected between said output and ground, wherein a portion of said transistors are turned on in accordance with said load control signal, adding impedance to said output.

42. The amplifier according to claim 33, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

43. The amplifier according to claim 33, adapted to be implemented in a Field Programmable Gate Array (FPGA).