Power saving in multi-processor device

• US 20070140199A1
• Filed: 12/05/2006
• Published: 06/21/2007
• Est. Priority Date: 02/25/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Palm, Inc. (TCL Technology Group Corp.)
• Inventors: Kammer, David, Ho, Alex Yee Kit, Chan, Bennett, Davis, Mark, Zhao, Wen, Mathias, Arun, Mahe, Isabel
• Granted Patent: US 7,898,994 B2
• Time in Patent Office: Days
• US Class Current: 370/338
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 52/287 when the channel is in stand-by
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A mobile computing device comprises a first microprocessor having a sleep mode and a wake mode and a second microprocessor configured for wireless communication. A communication port is configured to communicate data from the second processor to the first processor, wherein the second processor is configured to provide a wake signal to the first microprocessor and the first microprocessor is configured to open the communication port in response to the wake signal and to receive data from the second microprocessor through the communication port.

Claims

1. A mobile computing device, comprising:

a first microprocessor having a sleep mode and a wake mode;

a second microprocessor configured for wireless communication; and

;

a communication port configured to communicate data from the second processor to the first processor, wherein the second processor is configured to provide a wake signal to the first microprocessor and the first microprocessor is configured to open the communication port in response to the wake signal and to receive data from the second microprocessor through the communication port.

2. The mobile computing device of claim 1, wherein the communication port comprises a universal serial bus.

3. The mobile computing device of claim 2, wherein the second microprocessor is configured to communicate with the first microprocessor via a universal asynchronous receiver transmitter (UART).

4. The mobile computing device of claim 1, wherein the first microprocessor is configured to process the wake signal as an interrupt.

5. The mobile computing device of claim 4, wherein the second microprocessor is configured to de-assert the interrupt when the second microprocessor has completed transmission of the data.

6. The mobile computing device of claim 1, wherein the second microprocessor is a modem.

7. The mobile computing device of claim 1, wherein the first and second microprocessors are part of a dual-core chip.

8. The mobile computing device of claim 1, wherein the first processor, in response to the wake signal, is configured to send a signal to the second processor indicating the first processor is ready to receive data, wherein the second processor is configured to send the data in response to receiving the signal

9. The mobile computing device of claim 7, wherein the first processor is configured to provide a second wake signal to the second microprocessor, the second processor is configured to send a second signal to the first processor indicating the second processor is ready to receive second data, wherein the first processor is configured, in response to the second signal to send data to the second microprocessor through the communication port.

10. The mobile computing device of claim 1, wherein the second microprocessor is configured to pulse the wakeup signal during at least a portion of a time during which the first microprocessor is receiving data from the second microprocessor.

11. A mobile computing device, comprising:

a first microprocessor configured to operate a plurality of applications and having a sleep mode and a wake mode;

a second microprocessor configured to provide wireless communication over a network;

a universal serial bus; and

a universal serial bus controller having on, off and suspend states, the universal serial bus controller coupled to the first microprocessor and configured to provide universal serial bus communication with the second microprocessor, wherein after processing a message on the universal serial bus, the universal serial bus controller is configured to enter the off state while the first processor is in a sleep state.

12. The mobile computing device of claim 11, further comprising a serial communication bus controller coupled to the first microprocessor, the serial communication bus controller having an on state and an off state, wherein the universal serial bus controller is configured to be put in the off state when the serial communication bus controller is in the on state.

13. The mobile computing device of claim 11, wherein the universal serial bus controller is configured to move from the off to the on state without enumerating.

14. A mobile computing device for communicating with a network, the network of a type configured to release a channel of communication with a device after expiration of a timer, comprising:

a first microprocessor configured to operate a plurality of applications; and

a second microprocessor configured to provide wireless communication over the network, wherein the second microprocessor has a sleep mode and a wake mode, wherein the second microprocessor is configured to enter the sleep mode before expiration of the timer.

15. The mobile computing device of claim 14, wherein the second microprocessor is configured to provide wireless data communication with the network using a Code Division Multiple Access protocol.

16. The mobile computing device of claim 14, wherein the second microprocessor is configured to provide wireless data communication with the network having a dormancy timer between approximately 10 and 20 seconds.

17. The mobile computing device of claim 14, wherein the second microprocessor is configured to enter the sleep mode in response to a sleep signal from the first microprocessor.

18. The mobile computing device of claim 14, wherein the second microprocessor is configured to enter the sleep mode in response to a signal indicating the first microprocessor is entering a sleep state.

19. The mobile computing device of claim 14, wherein the first and second microprocessors are part of a dual-core integrated circuit.