Method of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors

• US 20070141821A1
• Filed: 02/09/2007
• Published: 06/21/2007
• Est. Priority Date: 12/03/2004
• Status: Active Grant

• Current Assignee: John Zahurak, Kunal Parekh
• Original Assignee: John Zahurak, Kunal Parekh
• Inventors: Zahurak, John, Parekh, Kunal
• Granted Patent: US 7,833,892 B2
• Time in Patent Office: Days
• US Class Current: 438/595
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

Claims

1-70. -70. (canceled)

71. A method of forming a field effect transistor, comprising:

forming a gate electrode of a field effect transistor over a silicon-comprising substrate, the gate electrode comprising a sidewall;

forming a first electrically insulative anisotropically etched sidewall spacer over the sidewall of the gate electrode;

forming a second anisotropically etched sidewall spacer over and distinct from the first sidewall spacer;

depositing metal over the first and second sidewall spacers and over silicon of a source/drain region of the transistor proximate the second sidewall spacer; and

annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide on the source/drain region which is spaced from the first sidewall spacer.

72. The method of claim 71 comprising removing the second sidewall spacer from the substrate after the annealing.

73. The method of claim 71 wherein the second sidewall spacer is formed on the first sidewall spacer.

74. The method of claim 71 comprising forming an intervening anisotropically etched sidewall spacer between the first and second anisotropically etched sidewall spacers.

75. The method of claim 71 wherein the second sidewall spacer is comprised of a material that is different from that of the first sidewall spacer.

76. The method of claim 75 wherein the second sidewall spacer comprises an electrically conductive material.

77. The method of claim 75 wherein the second sidewall spacer comprises an electrically insulative material.

78. The method of claim 71 wherein the second sidewall spacer is semiconductive.

79. The method of claim 71 wherein the metal is deposited on the second sidewall spacer.

80. The method of claim 71 wherein the metal is deposited on the first sidewall spacer.

81. The method of claim 71 wherein the silicide physically contacts the second sidewall spacer.

82. The method of claim 81 comprising removing the second sidewall spacer from the substrate after the annealing.