Clock-free activation circuit

• US 20070141983A1
• Filed: 12/15/2005
• Published: 06/21/2007
• Est. Priority Date: 12/15/2005
• Status: Active Grant

• Current Assignee: Zest Labs, Inc.
• Original Assignee: Intelleflex Corporation
• Inventors: Olah, Robert, Shyu, Jyn-Bang, Mittal, Rohit
• Granted Patent: US 8,548,098 B2
• Time in Patent Office: Days
• US Class Current: 455/41.100
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0332 with an integrator-detector

Abstract

A circuit for recovering data from an incoming data stream according to one embodiment includes a capacitor and a substantially constant current source for charging the capacitor. A subcircuit generates a signal causing the capacitor to discharge upon detecting a first type of transition in the incoming data stream, the capacitor re-charging upon being at least partially discharged. A comparator compares a voltage on a node coupled to the capacitor to a reference voltage, the comparator outputting a first signal if the voltage on the node is higher than the reference voltage and outputting a second signal if the voltage on the node is lower than the reference voltage, the first signal being associated with a first logic value, the second signal being associated with a second logic value.

Claims

1. A circuit, comprising:

a capacitor;

a substantially constant current source for charging the capacitor;

a subcircuit for generating a signal causing the capacitor to discharge upon detecting a first type of transition in the incoming data stream, the capacitor charging upon being at least partially discharged; and

a comparator for comparing a voltage on a node coupled to the capacitor to a reference voltage, the comparator outputting a first signal if the voltage on the node is higher than the reference voltage and outputting a second signal if the voltage on the node is lower than the reference voltage, the first signal being associated with a first logic value, the second signal being associated with a second logic value.

2. A circuit as recited in claim 1, further comprising logic for detecting a pattern in the incoming data stream based on the first and second signals.

3. A circuit as recited in claim 2, wherein the logic generates an interrupt upon detecting the pattern.

4. A circuit as recited in claim 3, further comprising additional circuitry being activated upon generation of the interrupt, the additional circuitry being for detecting an activate code in the incoming data stream.

5. A circuit as recited in claim 4, wherein the additional circuitry activates a host device upon detecting the activate code in the incoming data stream.

6. A circuit as recited in claim 1, wherein transitions in the incoming data stream are used to identify individual logic values.

7. A circuit as recited in claim 1, wherein the incoming data stream is a radio frequency signal.

8. A circuit as recited in claim 1, wherein the circuit is part of an activation system of a Radio Frequency Identification (RFID) tag.

9. A Radio Frequency Identification (RFID) system, comprising:

a plurality of RFID tags having the circuit of claim 1;

and

an RFID interrogator in communication with the RFID tags.

10. A circuit for recovering data from an incoming data stream, comprising:

a time-to-voltage converter for generating first and second signals based on transitions in an incoming data stream, the first signal being associated with a first logic value, the second signal being associated with a second logic value; and

logic for identifying transitions in the incoming data stream, the transitions being used to identify individual logic values from the first and second signals.

11. A circuit as recited in claim 10, wherein the circuit is part of an activation system of a Radio Frequency Identification (RFID) tag.

12. A Radio Frequency Identification (RFID) system, comprising:

a plurality of RFID tags having the circuit of claim 10;

and

an RFID interrogator in communication with the RFID tags.

13. A method for recovering data from an incoming data stream, comprising:

charging a capacitor;

sequentially performing the following sequence;

discharging the capacitor upon detecting a first type of transition in the incoming data stream;

charging the capacitor after the capacitor is at least partially discharged;

comparing a voltage on a node coupled to the capacitor to a reference voltage;

outputting a first signal if the voltage on the node is higher than the reference voltage, the first signal being associated with a first logic value; and

outputting a second signal if the voltage on the node is lower than the reference voltage, the second signal being associated with a second logic value.

14. A method as recited in claim 13, further comprising detecting a pattern in the incoming data stream based on the first and second signals.

15. A method as recited in claim 14, further comprising generating an interrupt upon detecting the pattern.

16. A method as recited in claim 15, further comprising activating additional circuitry upon generating the interrupt.

17. A method as recited in claim 16, further comprising using the additional circuitry to analyze the incoming data stream for detecting an activate code in the incoming data stream.

18. A method as recited in claim 16, further comprising wherein the additional circuitry activates a host device upon detecting an activate code in the incoming data stream.

19. A method as recited in claim 13, further comprising using transitions in the incoming data stream to identify individual logic values.

20. A method as recited in claim 13, wherein the incoming data stream is a radio frequency signal.

21. A Radio Frequency Identification (RFID) system, comprising:

a plurality of RFID tags performing the method of claim 13;

and

an RFID interrogator in communication with the RFID tags.

22. A method for recovering data in an incoming data stream, comprising:

using a time-to-voltage converter to generate first and second signals based on transitions in an incoming data stream;

outputting the first signal if the voltage of the time-to-voltage converter is higher than a reference voltage, the first signal being associated with a first logic value;

outputting a second signal if the voltage of the time-to-voltage converter is lower than the reference voltage, the second signal being associated with a second logic value; and

using transitions in the incoming data stream to identify individual logic values from the first and second signals.

23. A Radio Frequency Identification (RFID) system, comprising:

a plurality of RFID tags performing the method of claim 22;

and

an RFID interrogator in communication with the RFID tags.