Simulation method

• US 20070150248A1
• Filed: 12/04/2006
• Published: 06/28/2007
• Est. Priority Date: 12/02/2005
• Status: Active Grant

• Current Assignee: Derek Chiou
• Original Assignee: Derek Chiou
• Inventors: Chiou, Derek
• Granted Patent: US 7,840,397 B2
• Time in Patent Office: Days
• US Class Current: 703/13
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/4494 data driven

Abstract

A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Claims

1. A method of simulating comprising:

partitioning a simulator into a functional component and a behavior prediction component;

executing the functional and behavioral prediction components in parallel;

using the execution path of the functional component to drive the behavior prediction component; and

with the behavior prediction component changing the execution path of the functional component.

2. A method as claimed in claim 1, wherein at least one component is implemented in hardware.

3. A method as claimed in claim 2, wherein the hardware comprises a field programmable gate array (FPGA).

4. A method as claimed in claim 1, wherein the functional model is implemented in software.

5. A method as claimed in claim 4, wherein the behavior prediction model is implemented in hardware.

6. A method as claimed in claim 5, wherein the hardware comprises an FPGA.

7. A method as claimed in claim 6, wherein the simulator simulates a computer system.

8. A method as claimed in claim 1, wherein the behavior prediction component is a timing model that predicts performance.

12. A method as claimed in claim 1, wherein the functional model is implemented in software.

13. A method as claimed in claim 12, wherein the timing model is implemented in hardware.

14. A method as claimed in claim 13, wherein the hardware comprises an FPGA.

15. A method as claimed in claim 14, wherein the simulator simulates a computer system.

9. A method of simulating comprising:

partitioning a simulator into a functional component and a timing component;

executing the functional and behavioral prediction components in parallel;

using the output of the functional component to drive the timing component; and

with the timing component changing the execution path of the functional component.

10. A method as claimed in claim 9, wherein at least one component is implemented in hardware.

11. A method as claimed in claim 10, wherein the hardware comprises a field programmable gate array (FPGA).