Address translation device

• US 20070156935A1
• Filed: 01/03/2006
• Published: 07/05/2007
• Est. Priority Date: 01/03/2006
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ellison, Brandon
• Granted Patent: US 7,444,453 B2
• Time in Patent Office: Days
• US Class Current: 710/106
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

An apparatus, system and method to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The apparatus includes a detection module to detect an incoming address on the I2C bus, a translation module to translate the incoming address to an outgoing address, and a communication module to communicate data between the host device and the slave device where the outgoing address matches the physical address of the slave device. In this manner, the present invention avoids address conflicts between commonly addressed slave devices while reducing costs, components, and complexities traditionally associated with dynamic addressing techniques and other prior art solutions to address conflicts.

Claims

1. An apparatus to facilitate communication over an inter-integrated circuit (I2C) bus:

between a host device and a slave device, the slave device sharing a common physical address with at least one other slave device on the I2C bus, the apparatus comprising;

a detection module to detect an incoming address on an I2C bus;

a translation module to translate the incoming address to an outgoing address; and

a communication module to communicate data between a host device and a slave device in response to the outgoing address matching a physical address of the slave device.

2. The apparatus of claim 1, further comprising a correspondence module to uniquely correspond a translation device address to the physical address of the slave device.

3. The apparatus of claim 2, wherein the translation device address comprises more than one I2C address.

4. The apparatus of claim 2, wherein the correspondence module further comprises means for selectively dynamically modifying the translation device address.

5. The apparatus of claim 4, wherein the means for selectively modifying the translation device address comprises at least one of external pins and microcode.

6. The apparatus of claim 1, wherein the incoming address comprises a plurality of binary bits.

7. The apparatus of claim 6, wherein the translation module serially translates each of the plurality of binary bits.

8. The apparatus of claim 7, wherein the translation module flips the each binary bit in response to a mismatch between the each binary bit and a binary bit corresponding to a translation device address.

9. The apparatus of claim 1, wherein the communication module comprises a CMOS switch to selectively communicate data between the host device and the slave device.

10. A system to facilitate communication over an I2C bus between a host device and a slave device, the slave device sharing a common physical address with at least one other slave device on the I2C bus, the system comprising:

a host device;

a slave device in communication with the host device over an I2C bus, the slave device sharing a common physical address with at least one other slave device on the I2C bus; and

a translation device intermediate the host device and the slave device and connected to the I2C bus, the translation device comprising;

a detection module to detect an incoming address on the I2C bus;

a translation module to translate the incoming address to an outgoing address; and

a communication module to communicate data between the host device and the slave device in response to the outgoing address matching a physical address of the slave device.

11. The system of claim 10, wherein the host device is selected from the group consisting of a microcontroller, a microprocessor, and a management module.

12. The system of claim 10, wherein the slave device is selected from the group consisting of a RAM, an EEPROM and an I/O device.

13. The system of claim 10, wherein the translation device further comprises a correspondence module to uniquely correspond a translation device address to the physical address.

14. The system of claim 13, wherein the translation device address comprises more than one I2C address.

15. The system of claim 13, wherein the correspondence module further comprises means for selectively dynamically modifying the translation device address.

16. The system of claim 10, wherein the incoming address comprises a plurality of binary bits.

17. The system of claim 16, wherein the translation module serially translates each of the plurality of binary bits.

18. The system of claim 17, wherein the translation module flips the each binary bit in response to a mismatch between the each binary bit and a binary bit corresponding to the translation device address.

19. A method to facilitate communication over an I2C bus between a host device and a slave device, the slave device sharing a common physical address with at least one other slave device on the I2C bus, the method comprising:

detecting an incoming address on an I2C bus;

translating the incoming address to an outgoing address; and

communicating data between a host device and a slave device in response to the outgoing address matching a physical address of the slave device.

20. The method of claim 19, wherein translating further comprises flipping a binary bit of the outgoing address in response to a mismatch between a binary bit of the incoming address and a binary bit of a translation device address.