NAND-type non-volatile memory devices having a stacked structure and associated methods of forming and operating the same

• US 20070165455A1
• Filed: 12/12/2006
• Published: 07/19/2007
• Est. Priority Date: 12/12/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jae-Kwan, Kim, Ki-Nam, Jung, Soon-Moon
• Granted Patent: US 7,626,228 B2
• Time in Patent Office: Days
• US Class Current: 365/185.10
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

Claims

1. A NAND-type nonvolatile memory device, comprising:

a semiconductor substrate;

a first ground selection line and a first string selection line disposed on the substrate in parallel to each other;

a plurality of parallel first word lines interposed on the substrate between the first ground selection line and the first string selection line;

a first impurity-doped region formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line;

a first interlayer dielectric layer disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate;

an epitaxial contact plug that contacts the semiconductor substrate through the first interlayer dielectric layer;

a single crystalline semiconductor layer disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug;

a plurality of parallel second word lines disposed on the single crystalline semiconductor layer;

a second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines; and

a second interlayer dielectric layer disposed on the plurality of second word lines and the single crystalline semiconductor layer.

2. The NAND-type nonvolatile memory device of claim 1, wherein the first and the second word lines each comprise a tunnel insulation layer, a charge storage layer, a blocking insulation layer, and a gate electrode that are stacked sequentially.

3. The NAND-type nonvolatile memory device of claim 1, wherein the epitaxial contact plug comprises a first epitaxial contact plug that is located between the plurality of first word lines and the first ground selection line and a second epitaxial contact plug that is located between the plurality of first word lines and the first string selection line, the first epitaxial contact plug electrically connecting the first impurity-doped region between the plurality of first word lines and the first ground selection line to the second impurity-doped region on a first side of the second word lines and the second epitaxial contact plug electrically connecting the first impurity-doped region between the plurality of first word lines and the first string selection line to the second impurity-doped region on a second side of the second word lines.

4. The NAND-type nonvolatile memory device of claim 3, wherein the first string selection line comprises a plurality of first string selection lines, the device further comprising:

a bit line contact that contacts the first impurity-doped region between one of the first string selection lines and a neighboring one of the first string selection lines through the second interlayer dielectric layer and the first interlayer dielectric layer; and

a bit line disposed on the second interlayer dielectric layer that contacts the bit line contact.

5. The NAND-type nonvolatile memory device of claim 4, further comprising a device isolation layer that contacts the first interlayer dielectric layer through the single crystalline semiconductor layer to define an active region of the single crystalline layer;

wherein the bit line contact penetrates the second interlayer dielectric layer, the device isolation layer, and the first interlayer dielectric layer.

6. The NAND-type nonvolatile memory device of claim 3, further comprising:

an impurity-doped contact region in the single crystalline semiconductor layer between the second impurity-doped region and the epitaxial contact plug.

7. The NAND-type nonvolatile memory device of claim 1, wherein the first string selection line comprises a plurality of first string selection lines and the epitaxial contact plug is located between one of the first string selection lines and a neighboring one of first string selection lines, the device further comprising:

a second string selection line and a second ground selection line disposed on the single crystalline semiconductor layer.

8. The NAND-type nonvolatile memory device of claim 7, wherein the second string selection line comprises a plurality of second string selection lines, the device further comprising:

a bit line contact that contacts the second impurity-doped region between one of the second string selection lines and a neighboring one of second string selection lines through the second interlayer dielectric layer and electrically connects to the epitaxial contact plug; and

a bit line disposed on the second interlayer dielectric layer that contacts the bit line contact.

9. The NAND-type nonvolatile memory device of claim 7, further comprising:

an impurity-doped contact region in the single crystalline semiconductor layer between the second impurity-doped region and the epitaxial contact plug.

10. The NAND-type nonvolatile memory device of claim 7, wherein the first ground selection line comprises a plurality of first ground selection lines and the second ground selection line comprises a plurality of second ground selection lines, the device further comprising:

a first common source line disposed on the semiconductor substrate that contacts the first impurity-doped region between one of the first ground selection lines and a neighboring one of the first ground selection lines; and

a second common source line disposed on the single crystalline semiconductor layer that contacts the second impurity-doped region between one of the second ground selection lines and a neighboring one of the second ground selection lines;

wherein the first common source line is insulated from the second common source line.

11. A method of forming a NAND-type nonvolatile memory device, comprising:

providing a semiconductor substrate;

forming a first ground selection line and a first string selection line on the substrate in parallel to each other;

forming a plurality of parallel first word lines on the substrate between the first ground selection line and the first string selection line;

forming a first impurity-doped region formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line;

forming a first interlayer dielectric layer on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate;

patterning the first interlayer dielectric layer to form a hole that exposes the semiconductor substrate;

forming an epitaxial contact plug that contacts the semiconductor substrate in the hole;

forming a single crystalline semiconductor layer on the first interlayer dielectric layer that contacts the epitaxial contact plug;

forming a plurality of parallel second word lines on the single crystalline semiconductor layer;

forming a second impurity-doped region in the single crystalline semiconductor layer adjacent to the second word lines; and

forming a second interlayer dielectric layer on the plurality of second word lines and the single crystalline semiconductor layer.

12. The method of claim 11, wherein the first and the second word lines each comprise a tunnel insulation layer, a charge storage layer, a blocking insulation layer, and a gate electrode that are stacked sequentially.

13. The method of claim 11, wherein forming the epitaxial contact plug comprises forming a first epitaxial contact plug that is located between the plurality of first word lines and the first ground selection line and forming a second epitaxial contact plug that is located between the plurality of first word lines and the first string selection line, the first epitaxial contact plug electrically connecting the first impurity-doped region between the plurality of first word lines and the first ground selection line to the second impurity-doped region on a first side of the second word lines and the second epitaxial contact plug electrically connecting the first impurity-doped region between the plurality of first word lines and the first string selection line to the second impurity-doped region on a second side of the second word lines

14. The method of claim 13, wherein forming the first string selection line comprises forming a plurality of first string selection lines, the method further comprising:

forming a bit line contact that contacts the first impurity-doped region between one of the first string selection lines and a neighboring one of the first string selection lines through the second interlayer dielectric layer and the first interlayer dielectric layer; and

forming a bit line disposed on the second interlayer dielectric layer that contacts the bit line contact.

15. The method of claim 14, further comprising, after forming the single crystalline semiconductor layer:

forming a device isolation layer that contacts the first interlayer dielectric layer through the single crystalline semiconductor layer to define an active region of the single crystalline layer;

wherein the bit line contact penetrates the second interlayer dielectric layer, the device isolation layer, and the first interlayer dielectric layer

16. The method of claim 13, further comprising:

forming an impurity-doped contact region in the single crystalline semiconductor layer between the second impurity-doped region and the epitaxial contact plug.

17. The method of claim 11, forming the first string selection line comprises forming a plurality of first string selection lines and forming the epitaxial contact plug comprises forming the epitaxial contact plug between one of the first string selection lines and a neighboring one of first string selection lines, the method further comprising:

forming a second string selection line and a second ground selection line on the single crystalline semiconductor layer.

18. The method of claim 17, further comprising wherein forming the second string selection line comprises forming a plurality of second string selection lines, the method further comprising:

forming a bit line contact that contacts the second impurity-doped region between one of the second string selection lines and a neighboring one of second string selection lines through the second interlayer dielectric layer and electrically connects to the epitaxial contact plug; and

forming a bit line disposed on the second interlayer dielectric layer that contacts the bit line contact.

19. The method of claim 17, further comprising:

forming an impurity-doped contact region in the single crystalline semiconductor layer between the second impurity-doped region and the epitaxial contact plug.

20. The method of claim 17, wherein forming the first ground selection line comprises forming a plurality of first ground selection lines and forming the second ground selection line comprises forming a plurality of second ground selection lines, the method further comprising:

forming a first common source line on the semiconductor substrate that contacts the first impurity-doped region between one of the first ground selection lines and a neighboring one of the first ground selection lines; and

forming a second common source line on the single crystalline semiconductor layer that contacts the second impurity-doped region between one of the second ground selection lines and a neighboring one of the second ground selection lines;

wherein the first common source line is insulated from the second common source line.

21. A method of operating a NAND-type nonvolatile memory device, the memory device comprising a cell string, the cell string comprising a plurality of cell transistors, the plurality of cell transistors comprising a plurality of parallel sub-strings, a first one of the sub-strings comprising a first plurality of cell transistors connected to first word lines and a second one of the sub-strings comprising a second plurality of cell transistors connected to second word lines, a ground selection transistor is connected to a ground selection line on one side of the plurality of sub-strings, and a string selection transistor is connected to a string selection line on another side of the plurality of sub-strings, the method comprising:

reading a cell of the first one of the sub-strings by performing the following;

applying a read voltage to one of the first word lines associated with the cell of the first one of the sub-strings;

applying a pass voltage to the other ones of the first word lines connected to the first one of the sub-strings; and

applying a voltage of less than zero volts to the word lines connected to the second one of the sub-strings.

22. The method of claim 21, further comprising:

programming the cell of the first one of the sub-strings by performing the following;

applying a program voltage to the one of the first word lines associated with the cell of the first one of the sub-strings; and

applying a pass voltage to the other ones of the first word lines connected to the first one of the sub-strings.