CAPACITANCE-TO-DIGITAL INTERFACE CIRCUIT FOR DIFFERENTIAL PRESSURE SENSOR

• US 20070171107A1
• Filed: 01/26/2006
• Published: 07/26/2007
• Est. Priority Date: 01/26/2006
• Status: Active Grant

• Current Assignee: Fisher-Rosemount Systems Incorporated (Emerson Electric Company)
• Original Assignee: Fisher-Rosemount Systems Incorporated (Emerson Electric Company)
• Inventors: Wang, Rongtai
• Granted Patent: US 7,324,029 B2
• Time in Patent Office: Days
• US Class Current: 341/143
• CPC Class Codes: G01L 9/12 by making use of variations in capacitance , i.e. electric circuits therefor
• CPC Class Codes: H03M 3/356 Offset or drift compensation removal of offset already present on the analogue input signal H03M3/494
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/438 the modulator having a higher order loop filter in the feedforward path

Abstract

A two phase, second order capacitance-to-digital (CD) modulator includes a first stage sigma-delta integrator that forms charge packets as a function of sensor capacitance during an auto-zero phase and integrates the packets during an integration phase to produce an output voltage. The first stage integrator holds its output voltage during the auto-zero phase, so that a second stage sigma-delta integrator can sample the first stage output voltage during the auto-zero phase and integrate the sampled voltage during the integration phase.

Claims

1. A two-phase, second order capacitance-to-digital (CD) modulator for converting a first capacitance C_X and a second capacitance C_Y to a pulse code modulated (PCM) signal representative of (C_X-C_Y)/(C_X+C_Y), the CD modulator comprising:

a first stage sigma-delta integrator for selectively forming charge packets in C_X and C_Y during a first phase, and integrating charge from C_X and C_Y during a second phase to produce a first stage output V_OUT1, wherein the first stage sigma-delta integrator holds V_OUT1 constant during the first phase;

a second stage sigma-delta integrator for sampling the first stage output V_OUT1 during the first phase, and integrating the sampled first stage output during the second phase to produce a second stage output V_OUT2; and

a quantizer for converting the second stage output V_OUT2 to the PCM signal.

2. The CD modulator of claim 1 and further comprising:

a CD control unit for selectively providing an excitation signal to the first capacitance C_X and second capacitance C_Y as a function of the PCM signal.

3. The CD modulator of claim 2 wherein the first stage sigma-delta integrator comprises:

an integrator input node;

an amplifier having a first input, a second input and an output;

an auto-zero capacitor connected between the integrator input node and the first input of the amplifier;

a feedback capacitor connected to the output of the amplifier; and

a switching circuit for connecting C_X to the integrator input node when the PCM signal has a first state and C_Y to the integrator input node when the PCM signal has a second state, for connecting the feedback capacitor to the first input during the first phase, and for connecting the feedback capacitor to the common node during the second phase.

4. The CD modulator of claim 3 wherein the auto-zero capacitor stores a voltage that is a function of leakage resistance of C_X or C_Y during the first phase.

5. The CD modulator of claim 4, wherein the voltage stored by the auto-zero capacitor during the first phase causes the first stage integrator to saturate during the second phase if C_X is exposed to overpressure and is exhibiting a short circuit condition.

6. The CD modulator of claim 3 wherein the excitation signal switches between a first supply voltage level and a second supply voltage level as a function of the PCM signal states and the first and second phases.

7. The CD modulator of claim 6 wherein the second input of the amplifier is connected to receive the first supply voltage level.

8. The CD modulator of claim 7 wherein the switching circuit connects C_X to the first supply voltage level through a first protection resistance when the PCM signal is in the first state, connects C_Y to the first supply voltage level through a second protection resistance when the PCM signal is in a first state, and connects the integrator input node through a third protection resistance to the first supply voltage level during the first phase.

9. The CD modulator of claim 1 wherein the second stage sigma-delta integrator is resettable in response to a reset signal.

10. A two-phase, second order capacitance-to-digital (CD) modulator comprising:

a first stage sigma-delta integrator for selectively forming charge packets as a function of sensor capacitance during an auto-zero phase, and integrating the charge packets during an integration phase to produce a first stage output V_OUT1 that changes only in the integration phase;

a second stage sigma-delta integrator for sampling the first stage output V_OUT during the auto-zero phase, and integrating the sampled first stage output during the integration phase to produce a second stage output V_OUT2; and

a quantizer for converting the second stage output V_OUT2 to a pulse code modulated signal.

11. The CD modulator of claim 10 and further comprising:

a CD control unit for providing an excitation signal to produce the charge packets as a function of the PCM signal.

12. The CD modulator of claim 10 wherein the first stage sigma-delta integrator comprises:

an integrator input;

an amplifier having a first input, a second input and an output;

an auto-zero capacitor connected between the common node and the first input of the amplifier; and

a feedback capacitor connected to the output of the amplifier.

13. The CD modulator of claim 12 wherein the auto-zero capacitor stores a voltage that is a function of sensor leakage resistance during the auto-zero phase.

14. The CD modulator of claim 13 wherein the voltage stored by the auto-zero capacitor during the auto-zero phase causes the first stage sigma-delta integrator to saturate during the integration phase in an overpressure and short circuit condition.

15. A differential pressure transmitter comprising:

a first capacitance pressure sensor;

a second capacitance pressure sensor;

a first stage sigma-delta integrator for selectively forming charge packets as a function of capacitance of one of the first and second capacitance pressure sensors during a first phase, and integrating charge during a second phase to produce a first stage output V_OUT1, wherein the first stage output V_OUT1 is not reset between successive second phase periods;

a second stage sigma-delta integrator for sampling the first stage output V_OUT1 during the first phase, and integrating the sampled first stage output during the second phase to produce a second stage output V_OUT2; and

a quantizer for converting the second stage output V_OUT2 to a pulse code modulated (PCM) signal that is a function of pressure sensed by the first and second capacitance pressure sensors.

16. The differential pressure transmitter of claim 15 and further comprising:

an integrator input node;

an amplifier having a first input, a second input and an output;

an auto-zero capacitor connected between the integrator input node and the first input of the amplifier;

a feedback capacitor connected to the output of the amplifier; and

a switching circuit for connecting the first capacitance pressure sensor to the integrator input node when the PCM signal has a first state and the second capacitance pressure sensor to the integrator input when the PCM signal has a second state, for connecting the feedback capacitor to the first input during the first phase, and for connecting the feedback capacitor to the integrator input node during the second phase.

17. The differential pressure transmitter of claim 16 wherein the excitation signal switches between midlevel supply voltage and a low level supply voltage as a function of the PCM signal states and the first and second phases.

18. The differential pressure transmitter of claim 17 wherein the second input of the amplifier is connected to receive the midlevel supply voltage.

19. The differential pressure transmitter of claim 16 wherein the auto-zero capacitor stores a voltage that is a function of sensor leakage resistance during the first phase.

20. The differential pressure transmitter of claim 19 wherein the voltage stored by the auto-zero capacitor causes the first stage sigma-delta integrator to saturate during the integration phase if an overpressure and short circuit condition exists.