ISI reduction technique

• US 20070182476A1
• Filed: 09/20/2006
• Published: 08/09/2007
• Est. Priority Date: 02/08/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: van der Goes, Franciscus Maria Leonardus, Mulder, Jan, Ward, Christopher Michael
• Granted Patent: US 7,710,184 B2
• Time in Patent Office: Days
• US Class Current: 327/337
• CPC Class Codes: H03H 19/004 Switched capacitor networks

Abstract

The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.

Claims

1. A switch capacitor circuit with reduced Inter-Symbol-Interference effect comprising:

a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.

2. The switch capacitor circuit according to claim 1, wherein the at least one switch is further configured to be switched in a way that the first capacitor, after being discharged by means of the second capacitor, is charged to a second voltage by means of the voltage source.

3. The switch capacitor circuit according to claim 1, wherein the first capacitor and the second capacitor have the same capacitance.

4. A switch capacitor circuit with reduced Inter-Symbol-Interference effect comprising:

a voltage source, a first capacitor, a second capacitor, and at least one first switch configured to be switched in a way that

for a first time period, a first voltage exists across both the first and the second capacitor, and for a third time period, a second voltage exists across both the first and the second capacitor;

the circuit further comprising at least one pair of switches configured to be switched in a way that in a second time period between the first time period and the third time period, the first voltage existing across the second capacitor is reversed relative to the first voltage existing across the first capacitor, which causes the first capacitor to discharge through the second capacitor before being charged by the voltage source to the second voltage, thereby reducing the Inter-Symbol-Interference effect.

5. The switch capacitor circuit according to claim 4, wherein the first capacitor and the second capacitor have the same capacitance.

6. The switch capacitor circuit according to claim 4, wherein the at least one pair of switches comprise a first pair and a second pair of switches configured in a way that, when the first pair of switches change from a closed state to an open state and the second pair of switches change from a closed state to an open state, the voltage existing across the second capacitor is reversed relative to the voltage existing across the first capacitor.

7. A switch capacitor circuit with reduced Inter-Symbol-Interference effect comprising:

at least one voltage source, a first pair of capacitors comprising a first and a second capacitor and a second pair of capacitors comprising a third and a fourth capacitor and at least two pairs of switches configured to be switched in a way that,

for a first time period, a first voltage exists across the first and the second capacitor being connected in parallel, and a second voltage exists across the third and the fourth capacitor being connected in parallel, wherein the second voltage has the same absolute value as the first voltage, but is opposite in sign;

for a third time period, a third voltage exists across the first and the fourth capacitor, and a fourth voltage exists across the second and the third capacitor, wherein the fourth voltage has the same absolute value as the third voltage, but is opposite in sign;

in a second time period between the first time period and the third time period, the first capacitor is disconnected from the second capacitor and connected to the fourth capacitor, which causes the first capacitor to discharge through the fourth capacitor before the first and the fourth capacitor are charged by the at least one voltage source to the third voltage, thereby reducing the Inter-Symbol-Interference effect, and

the third capacitor is disconnected from the fourth capacitor and connected to the second capacitor, which causes the third capacitor to discharge through the second capacitor before the second and third capacitor are charged by the at least one voltage source to the fourth voltage, thereby reducing the Inter-Symbol-Interference effect.

8. The switch capacitor circuit according to claim 7, wherein the at least two pairs of switches are further configured to be switched in a way that,

in a fourth time period following the third time period, the first capacitor is disconnected from the fourth capacitor and connected to the second capacitor, which causes the first capacitor to discharge through the second capacitor, thereby reducing the Inter-Symbol-Interference effect, and

the third capacitor is disconnected from the second capacitor and connected to the fourth capacitor, which causes the third capacitor to discharge through the fourth capacitor, thereby reducing the Inter-Symbol-Interference effect.

9. The switch capacitor circuit according to claim 7, wherein the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor have all the same capacitance.

10. A method for reducing an Inter-Symbol-Interference effect in a switch capacitor circuit having a voltage source, a first capacitor and a second capacitor, the method comprising the steps of charging the first capacitor to a first voltage by means of the voltage source, and discharging the first capacitor by means of the second capacitor.

11. The method according to claim 10, wherein the step of charging the first capacitor further comprises charging the second capacitor to the first voltage and the step of discharging the first capacitor comprises reversing the first voltage existing across the second capacitor relative to the first voltage existing across the first capacitor and electrically connecting the first capacitor with the second capacitor.

12. The method according to claim 10, wherein the first capacitor and the second capacitor have the same capacitance.

13. The method according to claim 10, further comprising the step of charging the first capacitor to a second voltage by means of the voltage source after discharging the first capacitor.

14. The method according to claim 11, further comprising the step of charging the first capacitor and the second capacitor to a second voltage by means of the voltage source after discharging the first capacitor by means of the second capacitor.

15. A method for reducing an Inter-Symbol-Interference effect in a switch capacitor comprising at least one voltage source, a first pair of capacitors comprising a first and a second capacitor and a second pair of capacitors comprising a third and a fourth capacitor and at least two pair of switches, the method comprising the steps of:

charging the first and second capacitor to a first voltage by means of the at least one voltage source and charging the third and fourth capacitor to a second voltage by means of the at least one voltage source, wherein the second voltage has the same absolute value as the first voltage, but is opposite in sign;

disconnecting the first capacitor from the second capacitor and connecting the first capacitor to the fourth capacitor, which causes the first capacitor to discharge through the fourth capacitor;

disconnecting the third capacitor from the fourth capacitor and connecting the third capacitor to the second capacitor, which causes the third capacitor to discharge through the second capacitor.

16. The method according to claim 15, further comprising the step of charging the first and fourth capacitor to a third voltage and charging the second and third capacitor to a fourth voltage by means of the at least one voltage source, wherein the fourth voltage has the same absolute value as the third voltage, but is opposite in sign;

disconnecting the first capacitor from the fourth capacitor and connecting the first capacitor to the second capacitor, which causes the first capacitor to discharge through the second capacitor;

disconnecting the third capacitor from the second capacitor and connecting the third capacitor to the fourth capacitor, which causes the third capacitor to discharge through the fourth capacitor.

17. The method according to claim 15, wherein the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor have all the same capacitance.