Adaptive impedance matching module (AIMM) control architectures

• US 20070197180A1
• Filed: 01/16/2007
• Published: 08/23/2007
• Est. Priority Date: 01/14/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Paratek Microwave Incorporated (Blackberry Limited)
• Inventors: McKinzie, William, Mendolia, Greg, Bachmann, Heniz
• Granted Patent: US 7,711,337 B2
• Time in Patent Office: Days
• US Class Current: 455/248.1
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03H 7/40 Automatic matching of load impedance to source impedance
• CPC Class Codes: H04B 1/0458 Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages matching circuits in general H03H

Abstract

An embodiment of the present invention an apparatus, comprising an adaptive impedance matching module (AIMM) adapted to minimize the magnitude of an input reflection coefficient seen at an RF_in port under boundary conditions of a variable load impedance Z_L, a tuner connected to the AIMM and including a plurality of variable reactance networks with independent control signals, wherein node voltages are sampled within the tuner; and a microcontroller or digital signal processor (DSP) calculates complex reflection coefficient information from the sampled voltages, the microcontroller or DSP providing a coarse and fine tune function that feeds bias signals to control impedance matching.

Claims

2. The apparatus of claim 1, wherein said microcontroller or DSP chip samples the complex reflection coefficient information from at least one analog to digital converter (ADC).

1. An apparatus, comprising:

an adaptive impedance matching module (AIMM) adapted to minimize the magnitude of an input reflection coefficient seen at an RF_in port under boundary conditions of a variable load impedance Z_L;

a tuner connected to said AIMM and including a plurality of voltage tunable capacitors with independent control voltages, wherein backward-wave couplers sample incident and reflected waves respectively at the input side of said tuner; and

a microcontroller or digital signal process (DSP) chip to sample complex reflection coefficient information from said incident and reflected waves, said microcontroller or DSP providing a coarse tune function that feeds approximate bias voltages to control tuning.

3. The apparatus of claim 2, wherein said reflection coefficient phase angle is known and a look-up table is used to perform said coarse tune function that feeds approximate bias voltages to a plurality of digital to analog converters (DACs) that in turn control high voltage buffers driving said plurality of voltage tunable capacitors.

4. The apparatus of claim 2, wherein said microcontroller or DSP provide coarse tune function that feeds approximate bias voltages to a plurality of digital to analog converters (DACs) that in turn control high voltage buffers driving said plurality of voltage tunable capacitors.

5. The apparatus of claim 4, wherein if the magnitude of said reflection coefficient is not below a desired level, then fine tuning is accomplished using small and iterative adjustments in bias voltage.

6. The apparatus of claim 5, wherein said apparatus still further fine tunes as necessary to compensate for variations in manufacturing tolerances of tuner component values, or to compensate for temperature variations of the voltage tunable varactors under high power.

7. The apparatus of claim 5, wherein fine tuning is accomplished by using a fine tuning algorithm that is a scalar multi-variable minimization algorithm where the independent variables are the set of tuning voltages and a scalar cost function is the magnitude of the reflection coefficient in dB.

8. The apparatus of claim 3, further comprising a charge pump to multiply a typically available supply voltage to power said signal buffers.

9. The apparatus of claim 4, wherein said plurality of ADCs and DACs are integrated into the processor integrated circuit (IC).

10. The apparatus of claim 1, wherein said node voltages are switched such that they may be measured in sequence and controlled by said microcontroller or DSP.

11. The apparatus of claim 10, wherein output voltage, which is proportional to coupled power in dB, is digitized and the return loss is then calculated by said microcontroller or DSP using sequential measurements.

7-1. The apparatus of claim 6, wherein said minimization algorithm is selected from the group consisting of:

a downhill simplex method in multidimensions;

a conjugate gradient method in multidimensions;

or a quasi-Newton method.

12. An apparatus, comprising:

an adaptive antenna impedance matching module (AIMM) adapted to minimize the magnitude of an input reflection coefficient seen at an RF_in port under boundary conditions of a variable load impedance ZL;

a tuner connected to said AIMM and including a plurality of variable reactance networks with independent control signals, wherein an input impedance sensing circuit provides direct measurement of the ratio of the first two complex nodal voltages at the input side of said tuner; and

a microcontroller or digital signal processor (DSP) samples said complex node voltage ratio and calculates the complex input reflection coefficient and provides a tune function that feeds approximate bias signals to control.

13. The apparatus of claim 12, further comprising voltage variable capacitors for the variable reactance networks, and a look-up table used to immediately perform a coarse tune function that feeds approximate bias signals to DACs that in turn control voltage buffers for the voltage variable capacitors.

14. The apparatus of claim 12, wherein said input impedance sensing circuit consists of at least one known fixed reactive component on the input side of said tuner.

15. The apparatus of claim 12, wherein said apparatus still further fine tunes as necessary to compensate for variations in manufacturing tolerances of tuner component values, or to compensate for temperature variations of the voltage tunable varactors under high power.

16. The apparatus of claim 12, wherein fine tuning is accomplished by using a fine tuning algorithm that is a scalar multi-variable minimization algorithm where the independent variables are the set of tuning voltages and a scalar cost function is the magnitude of the reflection coefficient in dB.

17. The apparatus of claim 12, wherein said minimization algorithm is selected from the group consisting of:

a downhill simplex method in multidimensions;

a conjugate gradient method in multidimensions;

or

a quasi-Newton method.

18. The apparatus of claim 12, further comprising a charge pump to multiply a typically available supply voltage to power said signal buffers.

19. The apparatus of claim 12, wherein said plurality of ADCs and DACs are integrated into the processor integrated circuit (IC).

24. The apparatus of claim 12, wherein said reflection coefficient is used with a look-up table to perform said coarse tune function that feeds approximate bias signals to a plurality of digital to analog converters (DACs) that in turn control signal buffers driving said plurality of variable reactance networks.

25. The method of claim 24, wherein if the magnitude of said reflection coefficient is below a desired level, then fine tuning is accomplished using small and iterative adjustments in bias signals.

28. The apparatus of claim 12, wherein said variable reactance network comprises a voltage tunable dielectric capacitor.

20. The apparatus of claim 12, wherein said node voltages are switched such that they may be measured in sequence and controlled by said microcontroller or DSP.

21. The apparatus of claim 20, wherein magnitudes of said three node voltages are measured using a single channel log amp or temperature compensated diode detector.

20-2. An apparatus, comprising:

an adaptive antenna impedance matching module (AIMM) adapted to minimize the magnitude of an input reflection coefficient seen at an RF_in port under boundary conditions of a variable load impedance Z_L;

a tuner connected to said AIMM and including a plurality of variable reactance networks with independent bias control signals, wherein an RF voltage sensing circuit provides direct measurement of the magnitudes of three nodal voltages at the input side of said tuner; and

a microcontroller or digital signal processor (DSP) that calculates the AIMM input impedance from ratios of said node voltages, wherein three measurements of node voltage magnitude permit a unique determination of the input impedance for the tuner.

22. A method, comprising:

minimizing the magnitude of an input reflection coefficient seen at an RF_in , port under boundary conditions of a variable load impedance Z_L by an adaptive impedance matching module (AIMM) by using a tuner connected to said AIMM and including a plurality of variable reactance networks with independent bias control signals within said tuner, wherein two or more node voltages on the input side of the tuner are sampled ; and

using a microcontroller or digital signal processor (DSP) to calculate complex reflection coefficient information from said node voltages and providing by said microcontroller or DSP a tune function that feeds bias signals to control said variable reactance networks.

23. The method of claim 22, further comprising sampling the node voltage information from at least one analog to digital converter (ADC) by said microcontroller or DSP.

26. A machine-accessible medium that provides instructions, which when accessed, cause a machine to perform operations comprising:

minimizing the magnitude of an input reflection coefficient seen at an RF_in port under boundary conditions of a variable load impedance Z_L by an adaptive impedance matching module (AIMM) by using a tuner connected to said AIMM and including a plurality of variable reactance networks with independent control signals within said tuner, wherein two or more node voltages are sampled within said tuner; and

using a microcontroller or digital signal processor (DSP) to calculate complex reflection coefficient information from said node voltages and providing by said microcontroller or DSP a coarse tune function that feeds approximate bias signals to control said variable reactance networks.

27. The machine-accessible medium of claim 26, further comprising said instructions causing said machine to perform operations further sampling the node voltage information from at least one analog to digital converter (ADC) by said microcontroller or DSP.