METHOD FOR CONTROLLING POWER CONSUMPTION AND MULTI-PROCESSOR SYSTEM USING THE SAME
First Claim
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1. A multi-processor system, comprising:
- a clock generator for generating a plurality of clock signals with different speeds;
a clock controller for selecting one clock signal from the clock signals as a first clock signal in respond to a corresponding first control signal, and selecting multiple clock signals from the clock signals as a plurality of second clock signals in respond to a corresponding plurality of second control signals;
a main processor, using the first clock signal as the operation clock of the main processor, for outputting the first control signal according to the hardware performance of the main processor, wherein the clock controller is disabled when a disable signal outputted from the main processor is active;
a plurality of co-processors, using the second clock signals as the operation clocks of the co-processors respectively, for outputting the second control signals according to the hardware performances of the co-processors respectively, wherein each of the co-processors assists the main processor to perform a specific function operation; and
an interrupt control interface coupled among the main processor, the co-processors and the clock controller, for receiving an interrupt signal outputted from the main processor, at least one of the co-processors or the clock controller, and performing a corresponding interrupt operation.
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Abstract
A multi-processor system comprises a clock generator, a clock controller, a main processor, a plurality of co-processors and an interrupt control interface. Because the main processor and the co-processors need not work together to deliver the processing result, the multi-processor system may be designed that each processor in the multi-processor system is independently switched to operate at lower clock or power down completely according to the feedback of the hardware performance detection for each processor when the whole system is in active usage. This means on-demand power saving for the multi-processor system, so as to save power greatly.
36 Citations
9 Claims
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1. A multi-processor system, comprising:
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a clock generator for generating a plurality of clock signals with different speeds; a clock controller for selecting one clock signal from the clock signals as a first clock signal in respond to a corresponding first control signal, and selecting multiple clock signals from the clock signals as a plurality of second clock signals in respond to a corresponding plurality of second control signals; a main processor, using the first clock signal as the operation clock of the main processor, for outputting the first control signal according to the hardware performance of the main processor, wherein the clock controller is disabled when a disable signal outputted from the main processor is active; a plurality of co-processors, using the second clock signals as the operation clocks of the co-processors respectively, for outputting the second control signals according to the hardware performances of the co-processors respectively, wherein each of the co-processors assists the main processor to perform a specific function operation; and an interrupt control interface coupled among the main processor, the co-processors and the clock controller, for receiving an interrupt signal outputted from the main processor, at least one of the co-processors or the clock controller, and performing a corresponding interrupt operation. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for controlling the power consumption for a multi-processor system with a plurality of co-processors, the method comprising:
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one of the co-processors is operated at a first speed; the co-processor is switched to be idle when the hardware performance of the co-processor is detected that the task has been completed; the co-processor is switched to operate at a second speed when the hardware performance of the co-processor is detected that part of the task has been completed, wherein the first speed is faster than the second speed; the co-processor is switched to be idle when the co-processor is operated at the second speed and the hardware performance of the co-processor is detected that the task has been completed; the co-processor is switched to operate at the first speed when the co-processor is operated at the second speed and the hardware performance of the co-processor is detected that the task increases; and the co-processor is switched to operate at the first speed when the co-processor is idle and receives an interrupt signal. - View Dependent Claims (8, 9)
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Specification
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Current AssigneeIte Tech (ITE Technologies Incorporated)
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Original AssigneeIte Tech (ITE Technologies Incorporated)
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InventorsWu, Yan, Tsao, Weisung, Chang, Wei-Lung, Cheng, Hown
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Application NumberUS11/461,440Publication NumberTime in Patent OfficeDaysField of SearchUS Class Current713/500CPC Class CodesG06F 1/3203 Power management, i.e. even...G06F 1/3287 by switching off individual...G06F 9/544 Buffers; Shared memory; PipesY02D 10/00 Energy efficient computing,...
