Nonvolatile semiconductor memory device
First Claim
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1. A nonvolatile semiconductor memory device comprising:
- a semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other;
a first insulating layer over the channel formation region;
a floating gate over the channel formation region with the first insulating layer interposed therebetween;
a second insulating layer over the floating gate; and
a control gate over the floating gate with the second insulating layer interposed therebetween,wherein the floating gate includes a semiconductor material, anda band gap of the semiconductor material is smaller than a band gap of the semiconductor layer.
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Abstract
A semiconductor layer having a channel formation region provided between a pair of impurity regions spaced from each other is provided, and a first insulating layer a floating gate, a second insulating layer, and a control gate are provided above the semiconductor layer. The semiconductor material forming the floating gate preferably has a band gap smaller than that of the semiconductor layer. The band gap of a channel formation region in the semiconductor material forming the floating gate is preferably smaller than that of the semiconductor layer by 0.1 eV or more.
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Citations
53 Claims
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1. A nonvolatile semiconductor memory device comprising:
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a semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other; a first insulating layer over the channel formation region; a floating gate over the channel formation region with the first insulating layer interposed therebetween; a second insulating layer over the floating gate; and a control gate over the floating gate with the second insulating layer interposed therebetween, wherein the floating gate includes a semiconductor material, and a band gap of the semiconductor material is smaller than a band gap of the semiconductor layer. - View Dependent Claims (6, 11, 16, 21, 24, 29, 34, 39, 44, 49)
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2. A nonvolatile semiconductor memory device comprising:
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a semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other; a first insulating layer over the channel formation region; a floating gate over the channel formation region with the first insulating layer interposed therebetween; a second insulating layer over the floating gate; and a control gate over the floating gate with the second insulating layer interposed therebetween, wherein the floating gate is formed from a material having a higher electron affinity than a material forming the semiconductor layer. - View Dependent Claims (7, 12, 17, 25, 30, 35, 40, 45, 50)
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3. A nonvolatile semiconductor memory device comprising:
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a semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other; a first insulating layer over the channel formation region; a floating gate over the channel formation region with the first insulating layer interposed therebetween; a second insulating layer over the floating gate; and a control gate over the floating gate with the second insulating layer interposed therebetween, wherein barrier energy formed by the first insulating layer for electrons of the floating gate is higher than barrier energy formed by the first insulating layer for electrons of the semiconductor layer. - View Dependent Claims (8, 13, 18, 26, 31, 36, 41, 46, 51)
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4. A nonvolatile semiconductor memory device comprising:
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a semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other; a first insulating layer over the channel formation region; a floating gate over the channel formation region with the first insulating layer interposed therebetween; a second insulating layer over the floating gate; and a control gate over the floating gate with the second insulating layer interposed therebetween, wherein the floating gate includes germanium or a germanium compound. - View Dependent Claims (9, 14, 19, 22, 27, 32, 37, 42, 47, 52)
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5. A nonvolatile semiconductor memory device comprising:
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a semiconductor layer having a channel formation region between a pair of impurity regions formed apart from each other; a first insulating layer over the channel formation region; a floating gate over the channel formation region with the first insulating layer interposed therebetween; a second insulating layer over the floating gate; and a control gate over the floating gate with the second insulating layer interposed therebetween, wherein the floating gate is formed of germanium or a germanium compound to a thickness of from 1 nm to 20 nm, inclusive. - View Dependent Claims (10, 15, 20, 23, 28, 33, 38, 43, 48, 53)
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Specification