Input buffer

• US 20070222484A1
• Filed: 03/23/2006
• Published: 09/27/2007
• Est. Priority Date: 03/23/2006
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Eldredge, Adam
• Granted Patent: US 7,348,809 B2
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2203/45008 the addition of two signals being made by a resistor addition circuit for producing the common mode signal
• CPC Class Codes: H03F 2203/45212 the differential amplifier being designed to have a reduced offset
• CPC Class Codes: H03F 2203/45654 the LC comprising one or more extra diodes not belonging to mirrors
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 2203/45722 the LC comprising one or more source followers, as post buffer or driver stages, in cascade in the LC
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45713 Controlling the active amplifying circuit of the differential amplifier
• CPC Class Codes: H03F 3/45744 by offset reduction
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

In one embodiment, the present invention includes an input buffer with a common gate amplifier having input terminals coupled to receive an incoming common mode voltage. The common gate amplifier may be configured to receive the incoming common mode voltage over a wide range of levels extending from a low end lower than a supply voltage of the input buffer to a high end exceeding the supply voltage.

Claims

1. An input buffer comprising:

a common gate amplifier having input terminals coupled to receive an incoming common mode voltage, wherein the common gate amplifier is configured to receive the incoming common mode voltage that can extend beyond a supply voltage of the input buffer.

2. The input buffer of claim 1, further comprising a bias circuit coupled to provide a bias voltage to gate terminals of the common gate amplifier, wherein the bias circuit is configured to provide the bias voltage at a level higher than the supply voltage.

3. The input buffer of claim 2, wherein the bias circuit is coupled to receive the incoming common mode voltage and to generate the bias voltage therefrom.

4. The input buffer of claim 3, wherein the bias circuit comprises a diode-connected current mirror transistor.

5. The input buffer of claim 1, wherein the common gate amplifier comprises a level shifter and a first gain stage coupled to directly receive the incoming common mode voltage from a driver circuit.

6. The input buffer of claim 5, further comprising a second gain stage coupled to output terminals of the first gain stage, the second gain stage configured to receive an output voltage of the first gain stage at a level lower than the supply voltage of the input buffer.

7. The input buffer of claim 6, further comprising a feedback circuit to receive an output voltage of the second gain stage and to control a gate voltage of a pair of input transistors of the first gain stage to introduce hysteresis.

8. The input buffer of claim 1, wherein the common gate amplifier comprises:

a pair of transistors having gate terminals commonly coupled, the pair of transistors having input terminals coupled to receive the incoming common mode voltage and output terminals coupled to provide an output voltage; and

a bias circuit to bias the gate terminals, wherein the bias circuit is coupled to receive the incoming common mode voltage and to generate the bias voltage therefrom.

9. The input buffer of claim 6, further comprising a voltage limiting circuit coupled to the output terminals of the first gain stage to limit the output voltage of the first gain stage to less than the supply voltage.

10. A method comprising:

receiving an input common mode voltage in an input buffer; and

directly amplifying and level shifting the input common mode voltage in a first gain stage of the input buffer from a first voltage that can extend beyond a supply voltage of the input buffer to a second voltage no larger than the supply voltage.

11. The method of claim 10, further comprising receiving the input common mode voltage at input terminals of a common gate amplifier of the first gain stage.

12. The method of claim 10, further comprising biasing the common gate amplifier using the input common mode voltage.

13. The method of claim 11, further comprising providing an output of the common gate amplifier to a second gain stage at the second voltage.

14. The method of claim 13, further comprising:

comparing an output of the second gain stage with a reference signal; and

controlling gate terminals of the common gate amplifier based on the comparison.

15. The method of claim 14, further comprising:

biasing a first transistor of the input buffer with a first bias voltage generated by a feedback circuit; and

biasing a second transistor of the input buffer with a second bias voltage generated by the feedback circuit, wherein the feedback circuit is gated by a feedback signal from the input buffer.

16. A system comprising:

a driver to transmit differential signals; and

a buffer coupled to the driver, the buffer having a first gain stage coupled to receive the differential signals, wherein the first gain stage is configured to receive the differential signals at a voltage level that can exceed a supply voltage of the buffer.

17. The system of claim 16, wherein the first gain stage comprises a common gate amplifier having input terminals coupled to receive the differential signals, wherein the differential signals are substantially greater than the supply voltage.

18. The system of claim 17, wherein the buffer further comprises a bias circuit coupled to provide a bias voltage to gate terminals of the common gate amplifier, wherein the bias circuit is coupled to receive the differential signals and to generate the bias voltage therefrom.

19. The system of claim 16, further comprising:

a physical media attach (PMA) device comprising a framer including the driver; and

a physical media dependent (PMD) device comprising a serializer/deserializer including the buffer.

20. The system of claim 16, further comprising:

a first integrated circuit (IC) coupled to a motherboard and to receive a first supply voltage therefrom, the first IC including the driver; and

a second IC including the buffer coupled to the motherboard and to receive the supply voltage of the buffer therefrom, wherein the first supply voltage is greater than the supply voltage of the buffer.

21. The system of claim 20, wherein the differential signals comprises low voltage positive emitter coupled logic (LVPECL) signals, and the buffer is to convert the LVPECL signals to low voltage differential signals.

22. An apparatus comprising:

means for receiving an input common mode voltage in an input buffer; and

gain stage means for directly amplifying and level shifting the input common mode voltage from a first voltage that can extend beyond a supply voltage of the input buffer to a second voltage no larger than the supply voltage.

23. The apparatus of claim 22, wherein the means for receiving comprises input terminals of a common gate amplifier of the gain stage means.

24. The apparatus of claim 23, further comprising means for biasing the common gate amplifier using the input common mode voltage.

25. The apparatus of claim 23, further comprising feedback means coupled to the common gate amplifier, the feedback means for comparing an output of a second gain stage means with a reference signal and controlling the common gate amplifier based on the comparing.